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Searched refs:AR934X_PLL_SWITCH_CLOCK_CONTROL_REG (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/mips/mach-ath79/
H A Dreset.c123 writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); in eth_init_ar934x()
125 writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); in eth_init_ar934x()
/openbmc/linux/arch/mips/ath79/
H A Dclock.c343 clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); in ar934x_clocks_init()
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h353 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 macro
/openbmc/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h316 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 macro