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Searched refs:APLL (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c33 case APLL: in s5pc100_get_pll_clk()
56 if (pllreg == APLL) in s5pc100_get_pll_clk()
84 case APLL: in s5pc110_get_pll_clk()
107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk()
120 if (pllreg == APLL) { in s5pc110_get_pll_clk()
146 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); in s5pc110_get_arm_clk()
168 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); in s5pc100_get_arm_clk()
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dapll.txt1 Binding for Texas Instruments APLL clock.
6 register-mapped APLL with usually two selectable input clocks
10 modes (locked, low power stop etc.) APLL mostly behaves like
20 - reg : address and length of the register set for controlling the APLL.
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk()
192 case APLL: in exynos4_get_pll_clk()
222 case APLL: in exynos4x12_get_pll_clk()
253 case APLL: in exynos5_get_pll_clk()
311 case APLL: in exynos542x_get_pll_clk()
584 armclk = get_pll_clk(APLL) / (core_ratio + 1); in exynos4_get_arm_clk()
606 armclk = get_pll_clk(APLL) / (core_ratio + 1); in exynos4x12_get_arm_clk()
628 armclk = get_pll_clk(APLL) / (arm_ratio + 1); in exynos5_get_arm_clk()
1580 sclk = get_pll_clk(APLL); in exynos4_get_i2c_clk()
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclk.h11 #define APLL 0 macro
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclk.h10 #define APLL 0 macro
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c355 APLL, enumerator
414 if (pll == APLL) in cpu_mux_select()
472 pll_init_one(APLL, JZ4780_APLL_M, JZ4780_APLL_N, JZ4780_APLL_OD); in pll_init()
/openbmc/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1-iot-512m.dts43 <&clk APLL>,
H A Dma35d1-som-256m.dts43 <&clk APLL>,
/openbmc/linux/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h14 #define APLL 2 macro
H A Dxlnx-versal-clk.h27 #define APLL 18 macro
H A Dnuvoton,ma35d1-clk.h22 #define APLL 11 macro
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A DREADME37 APLL: 600000000 DPLL:792000000 GPLL:384000000
/openbmc/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1-pll.c236 case APLL: in ma35d1_clk_pll_recalc_rate()
268 case APLL: in ma35d1_clk_pll_round_rate()
H A Dclk-ma35d1.c506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", in ma35d1_clocks_probe()
/openbmc/linux/drivers/clk/ingenic/
H A Djz4780-cgu.c295 .pll = DEF_PLL(APLL),
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt35 - 0 0 APLL
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3036.dtsi235 * Fix the emac parent clock is DPLL instead of APLL.