Searched refs:APLL (Results 1 – 17 of 17) sorted by relevance
/openbmc/u-boot/arch/arm/mach-s5pc1xx/ |
H A D | clock.c | 33 case APLL: in s5pc100_get_pll_clk() 56 if (pllreg == APLL) in s5pc100_get_pll_clk() 84 case APLL: in s5pc110_get_pll_clk() 107 if (pllreg == APLL || pllreg == MPLL) in s5pc110_get_pll_clk() 120 if (pllreg == APLL) { in s5pc110_get_pll_clk() 146 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); in s5pc110_get_arm_clk() 168 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); in s5pc100_get_arm_clk()
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
H A D | apll.txt | 1 Binding for Texas Instruments APLL clock. 6 register-mapped APLL with usually two selectable input clocks 10 modes (locked, low power stop etc.) APLL mostly behaves like 20 - reg : address and length of the register set for controlling the APLL.
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/openbmc/u-boot/arch/arm/mach-exynos/ |
H A D | clock.c | 125 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL || in exynos_get_pll_clk() 192 case APLL: in exynos4_get_pll_clk() 222 case APLL: in exynos4x12_get_pll_clk() 253 case APLL: in exynos5_get_pll_clk() 311 case APLL: in exynos542x_get_pll_clk() 584 armclk = get_pll_clk(APLL) / (core_ratio + 1); in exynos4_get_arm_clk() 606 armclk = get_pll_clk(APLL) / (core_ratio + 1); in exynos4x12_get_arm_clk() 628 armclk = get_pll_clk(APLL) / (arm_ratio + 1); in exynos5_get_arm_clk() 1580 sclk = get_pll_clk(APLL); in exynos4_get_i2c_clk()
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/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
H A D | clk.h | 11 #define APLL 0 macro
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/openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
H A D | clk.h | 10 #define APLL 0 macro
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/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/ |
H A D | pll.c | 355 APLL, enumerator 414 if (pll == APLL) in cpu_mux_select() 472 pll_init_one(APLL, JZ4780_APLL_M, JZ4780_APLL_N, JZ4780_APLL_OD); in pll_init()
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/openbmc/linux/arch/arm64/boot/dts/nuvoton/ |
H A D | ma35d1-iot-512m.dts | 43 <&clk APLL>,
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H A D | ma35d1-som-256m.dts | 43 <&clk APLL>,
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/openbmc/linux/include/dt-bindings/clock/ |
H A D | xlnx-zynqmp-clk.h | 14 #define APLL 2 macro
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H A D | xlnx-versal-clk.h | 27 #define APLL 18 macro
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H A D | nuvoton,ma35d1-clk.h | 22 #define APLL 11 macro
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/openbmc/u-boot/board/rockchip/evb_rv1108/ |
H A D | README | 37 APLL: 600000000 DPLL:792000000 GPLL:384000000
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/openbmc/linux/drivers/clk/nuvoton/ |
H A D | clk-ma35d1-pll.c | 236 case APLL: in ma35d1_clk_pll_recalc_rate() 268 case APLL: in ma35d1_clk_pll_round_rate()
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H A D | clk-ma35d1.c | 506 hws[APLL] = ma35d1_reg_clk_pll(dev, APLL, pllmode[2], "apll", in ma35d1_clocks_probe()
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/openbmc/linux/drivers/clk/ingenic/ |
H A D | jz4780-cgu.c | 295 .pll = DEF_PLL(APLL),
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/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/ |
H A D | cp110-system-controller.txt | 35 - 0 0 APLL
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/openbmc/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3036.dtsi | 235 * Fix the emac parent clock is DPLL instead of APLL.
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