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Searched refs:AMDGPU_VCN_STACK_SIZE (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c384 AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_3_mc_resume()
389 AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_3_mc_resume()
392 AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_3_mc_resume()
488 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
494 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
498 AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
952 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_3_start_sriov()
955 AMDGPU_VCN_STACK_SIZE; in vcn_v4_0_3_start_sriov()
H A Dvcn_v2_0.c365 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_mc_resume()
369 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
371 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
451 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
456 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
459 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1930 AMDGPU_VCN_STACK_SIZE); in vcn_v2_0_start_sriov()
1936 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_start_sriov()
1941 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_start_sriov()
H A Dvcn_v2_5.c448 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_mc_resume()
452 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
454 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
533 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
538 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
541 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1287 AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_sriov_start()
1292 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_sriov_start()
1297 AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_sriov_start()
H A Dvcn_v4_0.c407 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_mc_resume()
411 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
413 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v4_0_mc_resume()
502 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
507 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
510 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1310 AMDGPU_VCN_STACK_SIZE); in vcn_v4_0_start_sriov()
1313 AMDGPU_VCN_STACK_SIZE; in vcn_v4_0_start_sriov()
H A Dvcn_v3_0.c478 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_mc_resume()
482 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
484 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
562 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
567 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
570 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1374 AMDGPU_VCN_STACK_SIZE); in vcn_v3_0_start_sriov()
1377 AMDGPU_VCN_STACK_SIZE; in vcn_v3_0_start_sriov()
H A Dvcn_v1_0.c336 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v1_0_mc_resume_spg_mode()
340 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
342 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
407 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
412 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
415 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
H A Damdgpu_vcn.h29 #define AMDGPU_VCN_STACK_SIZE (128*1024) macro
H A Damdgpu_vcn.c172 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; in amdgpu_vcn_sw_init()