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Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 42) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_irq.c699 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()
730 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()
784 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_outbox_irq_state()
810 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_trace_irq_state()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_ai.c246 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()
306 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
H A Dmxgpu_nv.c264 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()
330 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
H A Damdgpu_irq.h43 AMDGPU_IRQ_STATE_ENABLE, enumerator
H A Dmxgpu_vi.c507 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()
545 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
H A Dnbio_v7_4.c465 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()
510 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
H A Dsi_dma.c600 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
616 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
H A Dsdma_v2_4.c1010 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1026 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
H A Damdgpu_irq.c530 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
H A Dvce_v2_0.c554 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
H A Dcik_sdma.c1117 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1133 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
H A Dnbio_v4_3.c561 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); in nbio_v4_3_set_ras_err_event_athub_irq_state()
H A Dsdma_v3_0.c1344 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
1360 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
H A Dgmc_v6_0.c1045 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
H A Dgfx_v9_0.c5722 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
5725 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()
5774 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
5792 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()
5795 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
5811 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()
5814 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
5846 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_cp_ecc_error_state()
H A Dgfx_v9_4_3.c2746 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
2767 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_reg_fault_state()
2771 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_reg_fault_state()
2790 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_4_3_set_priv_inst_fault_state()
2794 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_4_3_set_priv_inst_fault_state()
H A Dgfx_v6_0.c3210 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3239 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3273 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()
3298 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
H A Dgmc_v11_0.c77 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v11_0_vm_fault_interrupt_state()
H A Dvce_v3_0.c736 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
H A Dsdma_v4_4_2.c1521 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_4_2_set_trap_irq_state()
1617 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_4_2_set_ecc_irq_state()
H A Dgmc_v9_0.c445 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()
511 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
H A Dgfx_v7_0.c4671 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()
4722 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_compute_eop_interrupt_state()
4745 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_reg_fault_state()
4770 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_inst_fault_state()
H A Dgfx_v11_0.c5742 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_gfx_eop_interrupt_state()
5799 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_compute_eop_interrupt_state()
5904 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_reg_fault_state()
5907 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
5923 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v11_0_set_priv_inst_fault_state()
5926 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
H A Dgmc_v10_0.c82 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
H A Ddce_v8_0.c2923 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()
2974 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vline_interrupt_state()
3002 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_hpd_interrupt_state()

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