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Searched refs:ACC_RW (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/hw/net/fsl_etsec/
H A Dregisters.c31 {0x014, "IMASK", "Interrupt mask register", ACC_RW, 0x00000000},
32 {0x018, "EDIS", "Error disabled register", ACC_RW, 0x00000000},
33 {0x020, "ECNTRL", "Ethernet control register", ACC_RW, 0x00000040},
34 {0x028, "PTV", "Pause time value register", ACC_RW, 0x00000000},
35 {0x02C, "DMACTRL", "DMA control register", ACC_RW, 0x00000000},
36 {0x030, "TBIPA", "TBI PHY address register", ACC_RW, 0x00000000},
40 {0x058, "FIFO_RX_ALARM", "FIFO receive alarm start threshold register", ACC_RW, 0x00000…
41 {0x05C, "FIFO_RX_ALARM_SHUTOFF", "FIFO receive alarm shut-off threshold register", ACC_RW, 0x00000…
42 {0x08C, "FIFO_TX_THR", "FIFO transmit threshold register", ACC_RW, 0x00000…
43 {0x098, "FIFO_TX_STARVE", "FIFO transmit starve register", ACC_RW, 0x00000…
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H A Dmiim.c115 case ACC_RW: in etsec_write_miim()
H A Detsec.c94 case ACC_RW: in etsec_read()
263 case ACC_RW: in etsec_write()
H A Dregisters.h29 ACC_RW = 1, /* Read/Write */ enumerator