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/openbmc/qemu/docs/system/arm/
H A Drealview.rst5 the EB, PB-A8 and PBX-A9. Due to interactions with the bootloader, only
8 Kernels for the PB-A8 board should have CONFIG_REALVIEW_HIGH_PHYS_OFFSET
15 - ARM926E, ARM1136, ARM11MPCore, Cortex-A8 or Cortex-A9 MPCore CPU
H A Dcubieboard.rst5 which is a Cortex-A8 based single-board computer using
H A Dintegratorcp.rst6 - ARM926E, ARM1026E, ARM946E, ARM1136 or Cortex-A8 CPU
H A Dversatile.rst6 - ARM926E, ARM1136 or Cortex-A8 CPU
/openbmc/phosphor-webui/app/assets/icons/
H A Dicon-pending.svg1 …A8,8,0,0,1,13.12,14.13Zm-2.28,1.34a8.08,8.08,0,0,1-2.9.53V14.86a6.93,6.93,0,0,0,2.53-.48ZM3.48,13.…
/openbmc/u-boot/doc/
H A DREADME.s5pc1xx5 This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
15 While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
H A DREADME.omap35 This README is about U-Boot support for TI's ARM Cortex-A8 based OMAP3 [1]
6 family of SoCs. TI's OMAP3 SoC family contains an ARM Cortex-A8. Additionally,
/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Ddm-raid.rst129 A4 A4 A5 A6 A6 A7 A7 A8 A8
145 A3 A4 A4 A5 A6 A5 A6 A7 A8
146 A5 A6 A7 A8 A9 A9 A10 A11 A12
149 A4 A3 A6 A4 A5 A6 A5 A8 A7
150 A6 A5 A9 A7 A8 A10 A9 A12 A11
162 A3 A4 A4 A5 A6 A5 A6 A7 A8
163 A4 A3 A6 A4 A5 A6 A5 A8 A7
164 A5 A6 A7 A8 A9 A9 A10 A11 A12
165 A6 A5 A9 A7 A8 A10 A9 A12 A11
/openbmc/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7885-jackpotlte.dts3 * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source
16 model = "Samsung Galaxy A8 (2018)";
/openbmc/phosphor-webui/app/assets/images/
H A Dicon-search.svg1 …3.309 0 6 2.691 6 6s-2.691 6-6 6-6-2.691-6-6 2.691-6 6-6m0-2a8 8 0 1 0 0 16A8 8 0 0 0 9 1zM15 18l3…
/openbmc/u-boot/arch/arm/mach-omap2/
H A DKconfig82 The AM335x high performance SOC features a Cortex-A8
92 The AM335x high performance SOC features a Cortex-A8
130 The AM335x high performance SOC features a Cortex-A8
/openbmc/linux/arch/arm/mach-versatile/
H A DKconfig232 bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform"
236 Cortex(tm)-A8. This platform has an on-board Cortex-A8 and has
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa8.inc5 TUNEVALID[cortexa8] = "Enable Cortex-A8 specific processor optimizations"
/openbmc/linux/arch/arm/boot/dts/arm/
H A Darm-realview-pba8.dts27 model = "ARM RealView Platform Baseboard for Cortex-A8";
/openbmc/linux/Documentation/ABI/stable/
H A Dsysfs-class-tpm139 A7 1F 3C A8 D0 12 15 3E CA 0E BD FA 24 CD 33 C6
144 F7 02 71 CF 15 AE 16 DD D1 C1 8E A8 CF 9B 50 7B
/openbmc/linux/Documentation/arch/arm/
H A Dsunxi.rst20 * ARM Cortex-A8 based SoCs
/openbmc/linux/arch/arm/crypto/
H A Dsha1-armv4-large.S50 @ issue Cortex A8 core was measured to process input block in
56 @ Cortex A8 core and in absolute terms ~870 cycles per input block
62 @ improvement on Cortex A8 core and 12.2 cycles per byte.
/openbmc/linux/drivers/pinctrl/aspeed/
H A Dpinctrl-aspeed-g4.c471 #define A8 56 macro
474 SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S);
475 SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC);
476 PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
527 FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
1855 A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19,
1926 ASPEED_PINCTRL_PIN(A8),
2454 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
2455 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
H A Dpinctrl-aspeed-g5.c1859 #define A8 233 macro
1860 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
1861 SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
1862 PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN));
1864 FUNC_GROUP_DECL(USB2AH, A7, A8);
1865 FUNC_GROUP_DECL(USB2AD, A7, A8);
1921 ASPEED_PINCTRL_PIN(A8),
/openbmc/linux/Documentation/hwmon/
H A Dk10temp.rst20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-som-p0.dtsi99 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
/openbmc/linux/Documentation/admin-guide/media/
H A Dvisl.rst153 00000040: e8c3 4320 b4ba a226 cbc1 4138 3a12 32d6 ..C ...&..A8:.2.
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A DKconfig107 incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
/openbmc/qemu/pc-bios/
H A Dqemu.rsrc93 $"D2E6 F4FD 82FE 07FA DD30 31CB D75C 12A8" /* “ÊÙ˝Ç˛.˙›01À◊\.® */
173 $"00A8 00FF 00FF 00B0 000F 0812 2236 454D" /* .®.ˇ.ˇ.∞...."6EM */
217 $"A7A8 A6A6 85A8 00A7 81A6 02AD 6904 AF00" /* ß®¶¶Ö®.ßŶ.≠i.Ø. */
248 $"5358 6471 797B 7B81 7A04 7B79 7F5E 03A8" /* SXdqy{{Åz.{y.^.® */
256 $"7080 6F02 7062 51A8 521D 5353 524E 4536" /* pÄo.pbQ®R.SSRNE6 */
266 $"BE52 0954 5039 100E 3D53 5D63 18A8 0001" /* æR∆TP9..=S]c.®.. */
273 $"5680 5504 5656 584D 07A8 0001 2256 8052" /* VÄU.VVXM.®.."VÄR */
365 $"14D7 DFDF DDA5 45A8 C1A4 7E43 4DB0 DED6" /* .◊flfl›•E®¡§~CM∞fi÷ */
412 $"7A04 7B79 7F5E 03A8 0001 437E 8077 8176" /* z.{y.^.®..C~ÄwÅv */
/openbmc/linux/arch/arm/mm/
H A Dproc-v7.S499 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
589 @ Cortex-A8 - always needs bpiall switch_mm implementation

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