1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8450-videocc.h> 8#include <dt-bindings/clock/qcom,sm8550-gcc.h> 9#include <dt-bindings/clock/qcom,sm8550-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 11#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 }; 43 44 bi_tcxo_div2: bi-tcxo-div2-clk { 45 #clock-cells = <0>; 46 compatible = "fixed-factor-clock"; 47 clocks = <&rpmhcc RPMH_CXO_CLK>; 48 clock-mult = <1>; 49 clock-div = <2>; 50 }; 51 52 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 53 #clock-cells = <0>; 54 compatible = "fixed-factor-clock"; 55 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 56 clock-mult = <1>; 57 clock-div = <2>; 58 }; 59 60 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 }; 64 }; 65 66 cpus { 67 #address-cells = <2>; 68 #size-cells = <0>; 69 70 CPU0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a510"; 73 reg = <0 0>; 74 clocks = <&cpufreq_hw 0>; 75 enable-method = "psci"; 76 next-level-cache = <&L2_0>; 77 power-domains = <&CPU_PD0>; 78 power-domain-names = "psci"; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 capacity-dmips-mhz = <1024>; 81 dynamic-power-coefficient = <100>; 82 #cooling-cells = <2>; 83 L2_0: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 next-level-cache = <&L3_0>; 88 L3_0: l3-cache { 89 compatible = "cache"; 90 cache-level = <3>; 91 cache-unified; 92 }; 93 }; 94 }; 95 96 CPU1: cpu@100 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a510"; 99 reg = <0 0x100>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_100>; 103 power-domains = <&CPU_PD1>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 capacity-dmips-mhz = <1024>; 107 dynamic-power-coefficient = <100>; 108 #cooling-cells = <2>; 109 L2_100: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&L3_0>; 114 }; 115 }; 116 117 CPU2: cpu@200 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a510"; 120 reg = <0 0x200>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 next-level-cache = <&L2_200>; 124 power-domains = <&CPU_PD2>; 125 power-domain-names = "psci"; 126 qcom,freq-domain = <&cpufreq_hw 0>; 127 capacity-dmips-mhz = <1024>; 128 dynamic-power-coefficient = <100>; 129 #cooling-cells = <2>; 130 L2_200: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 next-level-cache = <&L3_0>; 135 }; 136 }; 137 138 CPU3: cpu@300 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a715"; 141 reg = <0 0x300>; 142 clocks = <&cpufreq_hw 1>; 143 enable-method = "psci"; 144 next-level-cache = <&L2_300>; 145 power-domains = <&CPU_PD3>; 146 power-domain-names = "psci"; 147 qcom,freq-domain = <&cpufreq_hw 1>; 148 capacity-dmips-mhz = <1792>; 149 dynamic-power-coefficient = <270>; 150 #cooling-cells = <2>; 151 L2_300: l2-cache { 152 compatible = "cache"; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&L3_0>; 156 }; 157 }; 158 159 CPU4: cpu@400 { 160 device_type = "cpu"; 161 compatible = "arm,cortex-a715"; 162 reg = <0 0x400>; 163 clocks = <&cpufreq_hw 1>; 164 enable-method = "psci"; 165 next-level-cache = <&L2_400>; 166 power-domains = <&CPU_PD4>; 167 power-domain-names = "psci"; 168 qcom,freq-domain = <&cpufreq_hw 1>; 169 capacity-dmips-mhz = <1792>; 170 dynamic-power-coefficient = <270>; 171 #cooling-cells = <2>; 172 L2_400: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU5: cpu@500 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a710"; 183 reg = <0 0x500>; 184 clocks = <&cpufreq_hw 1>; 185 enable-method = "psci"; 186 next-level-cache = <&L2_500>; 187 power-domains = <&CPU_PD5>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 1>; 190 capacity-dmips-mhz = <1792>; 191 dynamic-power-coefficient = <270>; 192 #cooling-cells = <2>; 193 L2_500: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU6: cpu@600 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a710"; 204 reg = <0 0x600>; 205 clocks = <&cpufreq_hw 1>; 206 enable-method = "psci"; 207 next-level-cache = <&L2_600>; 208 power-domains = <&CPU_PD6>; 209 power-domain-names = "psci"; 210 qcom,freq-domain = <&cpufreq_hw 1>; 211 capacity-dmips-mhz = <1792>; 212 dynamic-power-coefficient = <270>; 213 #cooling-cells = <2>; 214 L2_600: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "arm,cortex-x3"; 225 reg = <0 0x700>; 226 clocks = <&cpufreq_hw 2>; 227 enable-method = "psci"; 228 next-level-cache = <&L2_700>; 229 power-domains = <&CPU_PD7>; 230 power-domain-names = "psci"; 231 qcom,freq-domain = <&cpufreq_hw 2>; 232 capacity-dmips-mhz = <1894>; 233 dynamic-power-coefficient = <588>; 234 #cooling-cells = <2>; 235 L2_700: l2-cache { 236 compatible = "cache"; 237 cache-level = <2>; 238 cache-unified; 239 next-level-cache = <&L3_0>; 240 }; 241 }; 242 243 cpu-map { 244 cluster0 { 245 core0 { 246 cpu = <&CPU0>; 247 }; 248 249 core1 { 250 cpu = <&CPU1>; 251 }; 252 253 core2 { 254 cpu = <&CPU2>; 255 }; 256 257 core3 { 258 cpu = <&CPU3>; 259 }; 260 261 core4 { 262 cpu = <&CPU4>; 263 }; 264 265 core5 { 266 cpu = <&CPU5>; 267 }; 268 269 core6 { 270 cpu = <&CPU6>; 271 }; 272 273 core7 { 274 cpu = <&CPU7>; 275 }; 276 }; 277 }; 278 279 idle-states { 280 entry-method = "psci"; 281 282 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "silver-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <550>; 287 exit-latency-us = <750>; 288 min-residency-us = <6700>; 289 local-timer-stop; 290 }; 291 292 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 293 compatible = "arm,idle-state"; 294 idle-state-name = "gold-rail-power-collapse"; 295 arm,psci-suspend-param = <0x40000004>; 296 entry-latency-us = <600>; 297 exit-latency-us = <1300>; 298 min-residency-us = <8136>; 299 local-timer-stop; 300 }; 301 302 PRIME_CPU_SLEEP_0: cpu-sleep-2-0 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "goldplus-rail-power-collapse"; 305 arm,psci-suspend-param = <0x40000004>; 306 entry-latency-us = <500>; 307 exit-latency-us = <1350>; 308 min-residency-us = <7480>; 309 local-timer-stop; 310 }; 311 }; 312 313 domain-idle-states { 314 CLUSTER_SLEEP_0: cluster-sleep-0 { 315 compatible = "domain-idle-state"; 316 arm,psci-suspend-param = <0x41000044>; 317 entry-latency-us = <750>; 318 exit-latency-us = <2350>; 319 min-residency-us = <9144>; 320 }; 321 322 CLUSTER_SLEEP_1: cluster-sleep-1 { 323 compatible = "domain-idle-state"; 324 arm,psci-suspend-param = <0x4100c344>; 325 entry-latency-us = <2800>; 326 exit-latency-us = <4400>; 327 min-residency-us = <10150>; 328 }; 329 }; 330 }; 331 332 firmware { 333 scm: scm { 334 compatible = "qcom,scm-sm8550", "qcom,scm"; 335 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 336 }; 337 }; 338 339 clk_virt: interconnect-0 { 340 compatible = "qcom,sm8550-clk-virt"; 341 #interconnect-cells = <2>; 342 qcom,bcm-voters = <&apps_bcm_voter>; 343 }; 344 345 mc_virt: interconnect-1 { 346 compatible = "qcom,sm8550-mc-virt"; 347 #interconnect-cells = <2>; 348 qcom,bcm-voters = <&apps_bcm_voter>; 349 }; 350 351 memory@a0000000 { 352 device_type = "memory"; 353 /* We expect the bootloader to fill in the size */ 354 reg = <0 0xa0000000 0 0>; 355 }; 356 357 pmu { 358 compatible = "arm,armv8-pmuv3"; 359 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 360 }; 361 362 psci { 363 compatible = "arm,psci-1.0"; 364 method = "smc"; 365 366 CPU_PD0: power-domain-cpu0 { 367 #power-domain-cells = <0>; 368 power-domains = <&CLUSTER_PD>; 369 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 370 }; 371 372 CPU_PD1: power-domain-cpu1 { 373 #power-domain-cells = <0>; 374 power-domains = <&CLUSTER_PD>; 375 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 376 }; 377 378 CPU_PD2: power-domain-cpu2 { 379 #power-domain-cells = <0>; 380 power-domains = <&CLUSTER_PD>; 381 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 382 }; 383 384 CPU_PD3: power-domain-cpu3 { 385 #power-domain-cells = <0>; 386 power-domains = <&CLUSTER_PD>; 387 domain-idle-states = <&BIG_CPU_SLEEP_0>; 388 }; 389 390 CPU_PD4: power-domain-cpu4 { 391 #power-domain-cells = <0>; 392 power-domains = <&CLUSTER_PD>; 393 domain-idle-states = <&BIG_CPU_SLEEP_0>; 394 }; 395 396 CPU_PD5: power-domain-cpu5 { 397 #power-domain-cells = <0>; 398 power-domains = <&CLUSTER_PD>; 399 domain-idle-states = <&BIG_CPU_SLEEP_0>; 400 }; 401 402 CPU_PD6: power-domain-cpu6 { 403 #power-domain-cells = <0>; 404 power-domains = <&CLUSTER_PD>; 405 domain-idle-states = <&BIG_CPU_SLEEP_0>; 406 }; 407 408 CPU_PD7: power-domain-cpu7 { 409 #power-domain-cells = <0>; 410 power-domains = <&CLUSTER_PD>; 411 domain-idle-states = <&PRIME_CPU_SLEEP_0>; 412 }; 413 414 CLUSTER_PD: power-domain-cluster { 415 #power-domain-cells = <0>; 416 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 417 }; 418 }; 419 420 reserved_memory: reserved-memory { 421 #address-cells = <2>; 422 #size-cells = <2>; 423 ranges; 424 425 hyp_mem: hyp-region@80000000 { 426 reg = <0 0x80000000 0 0xa00000>; 427 no-map; 428 }; 429 430 cpusys_vm_mem: cpusys-vm-region@80a00000 { 431 reg = <0 0x80a00000 0 0x400000>; 432 no-map; 433 }; 434 435 hyp_tags_mem: hyp-tags-region@80e00000 { 436 reg = <0 0x80e00000 0 0x3d0000>; 437 no-map; 438 }; 439 440 xbl_sc_mem: xbl-sc-region@d8100000 { 441 reg = <0 0xd8100000 0 0x40000>; 442 no-map; 443 }; 444 445 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { 446 reg = <0 0x811d0000 0 0x30000>; 447 no-map; 448 }; 449 450 /* merged xbl_dt_log, xbl_ramdump, aop_image */ 451 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { 452 reg = <0 0x81a00000 0 0x260000>; 453 no-map; 454 }; 455 456 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 457 compatible = "qcom,cmd-db"; 458 reg = <0 0x81c60000 0 0x20000>; 459 no-map; 460 }; 461 462 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ 463 aop_config_merged_mem: aop-config-merged-region@81c80000 { 464 reg = <0 0x81c80000 0 0x74000>; 465 no-map; 466 }; 467 468 /* secdata region can be reused by apps */ 469 smem: smem@81d00000 { 470 compatible = "qcom,smem"; 471 reg = <0 0x81d00000 0 0x200000>; 472 hwlocks = <&tcsr_mutex 3>; 473 no-map; 474 }; 475 476 adsp_mhi_mem: adsp-mhi-region@81f00000 { 477 reg = <0 0x81f00000 0 0x20000>; 478 no-map; 479 }; 480 481 global_sync_mem: global-sync-region@82600000 { 482 reg = <0 0x82600000 0 0x100000>; 483 no-map; 484 }; 485 486 tz_stat_mem: tz-stat-region@82700000 { 487 reg = <0 0x82700000 0 0x100000>; 488 no-map; 489 }; 490 491 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { 492 reg = <0 0x82800000 0 0x4600000>; 493 no-map; 494 }; 495 496 mpss_mem: mpss-region@8a800000 { 497 reg = <0 0x8a800000 0 0x10800000>; 498 no-map; 499 }; 500 501 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { 502 reg = <0 0x9b000000 0 0x80000>; 503 no-map; 504 }; 505 506 ipa_fw_mem: ipa-fw-region@9b080000 { 507 reg = <0 0x9b080000 0 0x10000>; 508 no-map; 509 }; 510 511 ipa_gsi_mem: ipa-gsi-region@9b090000 { 512 reg = <0 0x9b090000 0 0xa000>; 513 no-map; 514 }; 515 516 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { 517 reg = <0 0x9b09a000 0 0x2000>; 518 no-map; 519 }; 520 521 spss_region_mem: spss-region@9b100000 { 522 reg = <0 0x9b100000 0 0x180000>; 523 no-map; 524 }; 525 526 /* First part of the "SPU secure shared memory" region */ 527 spu_tz_shared_mem: spu-tz-shared-region@9b280000 { 528 reg = <0 0x9b280000 0 0x60000>; 529 no-map; 530 }; 531 532 /* Second part of the "SPU secure shared memory" region */ 533 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { 534 reg = <0 0x9b2e0000 0 0x20000>; 535 no-map; 536 }; 537 538 camera_mem: camera-region@9b300000 { 539 reg = <0 0x9b300000 0 0x800000>; 540 no-map; 541 }; 542 543 video_mem: video-region@9bb00000 { 544 reg = <0 0x9bb00000 0 0x700000>; 545 no-map; 546 }; 547 548 cvp_mem: cvp-region@9c200000 { 549 reg = <0 0x9c200000 0 0x700000>; 550 no-map; 551 }; 552 553 cdsp_mem: cdsp-region@9c900000 { 554 reg = <0 0x9c900000 0 0x2000000>; 555 no-map; 556 }; 557 558 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { 559 reg = <0 0x9e900000 0 0x80000>; 560 no-map; 561 }; 562 563 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { 564 reg = <0 0x9e980000 0 0x80000>; 565 no-map; 566 }; 567 568 adspslpi_mem: adspslpi-region@9ea00000 { 569 reg = <0 0x9ea00000 0 0x4080000>; 570 no-map; 571 }; 572 573 /* uefi region can be reused by apps */ 574 575 /* Linux kernel image is loaded at 0xa8000000 */ 576 577 rmtfs_mem: rmtfs-region@d4a80000 { 578 compatible = "qcom,rmtfs-mem"; 579 reg = <0x0 0xd4a80000 0x0 0x280000>; 580 no-map; 581 582 qcom,client-id = <1>; 583 qcom,vmid = <15>; 584 }; 585 586 mpss_dsm_mem: mpss-dsm-region@d4d00000 { 587 reg = <0 0xd4d00000 0 0x3300000>; 588 no-map; 589 }; 590 591 tz_reserved_mem: tz-reserved-region@d8000000 { 592 reg = <0 0xd8000000 0 0x100000>; 593 no-map; 594 }; 595 596 cpucp_fw_mem: cpucp-fw-region@d8140000 { 597 reg = <0 0xd8140000 0 0x1c0000>; 598 no-map; 599 }; 600 601 qtee_mem: qtee-region@d8300000 { 602 reg = <0 0xd8300000 0 0x500000>; 603 no-map; 604 }; 605 606 ta_mem: ta-region@d8800000 { 607 reg = <0 0xd8800000 0 0x8a00000>; 608 no-map; 609 }; 610 611 tz_tags_mem: tz-tags-region@e1200000 { 612 reg = <0 0xe1200000 0 0x2740000>; 613 no-map; 614 }; 615 616 hwfence_shbuf: hwfence-shbuf-region@e6440000 { 617 reg = <0 0xe6440000 0 0x279000>; 618 no-map; 619 }; 620 621 trust_ui_vm_mem: trust-ui-vm-region@f3600000 { 622 reg = <0 0xf3600000 0 0x4aee000>; 623 no-map; 624 }; 625 626 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { 627 reg = <0 0xf80ee000 0 0x1000>; 628 no-map; 629 }; 630 631 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { 632 reg = <0 0xf80ef000 0 0x9000>; 633 no-map; 634 }; 635 636 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { 637 reg = <0 0xf80f8000 0 0x4000>; 638 no-map; 639 }; 640 641 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { 642 reg = <0 0xf80fc000 0 0x4000>; 643 no-map; 644 }; 645 646 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { 647 reg = <0 0xf8100000 0 0x100000>; 648 no-map; 649 }; 650 651 oem_vm_mem: oem-vm-region@f8400000 { 652 reg = <0 0xf8400000 0 0x4800000>; 653 no-map; 654 }; 655 656 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { 657 reg = <0 0xfcc00000 0 0x4000>; 658 no-map; 659 }; 660 661 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { 662 reg = <0 0xfcc04000 0 0x100000>; 663 no-map; 664 }; 665 666 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { 667 reg = <0 0xfce00000 0 0x2900000>; 668 no-map; 669 }; 670 671 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { 672 reg = <0 0xff700000 0 0x100000>; 673 no-map; 674 }; 675 }; 676 677 smp2p-adsp { 678 compatible = "qcom,smp2p"; 679 qcom,smem = <443>, <429>; 680 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 681 IPCC_MPROC_SIGNAL_SMP2P 682 IRQ_TYPE_EDGE_RISING>; 683 mboxes = <&ipcc IPCC_CLIENT_LPASS 684 IPCC_MPROC_SIGNAL_SMP2P>; 685 686 qcom,local-pid = <0>; 687 qcom,remote-pid = <2>; 688 689 smp2p_adsp_out: master-kernel { 690 qcom,entry-name = "master-kernel"; 691 #qcom,smem-state-cells = <1>; 692 }; 693 694 smp2p_adsp_in: slave-kernel { 695 qcom,entry-name = "slave-kernel"; 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 }; 699 }; 700 701 smp2p-cdsp { 702 compatible = "qcom,smp2p"; 703 qcom,smem = <94>, <432>; 704 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 705 IPCC_MPROC_SIGNAL_SMP2P 706 IRQ_TYPE_EDGE_RISING>; 707 mboxes = <&ipcc IPCC_CLIENT_CDSP 708 IPCC_MPROC_SIGNAL_SMP2P>; 709 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <5>; 712 713 smp2p_cdsp_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 smp2p_cdsp_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-modem { 726 compatible = "qcom,smp2p"; 727 qcom,smem = <435>, <428>; 728 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 729 IPCC_MPROC_SIGNAL_SMP2P 730 IRQ_TYPE_EDGE_RISING>; 731 mboxes = <&ipcc IPCC_CLIENT_MPSS 732 IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <1>; 736 737 smp2p_modem_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_modem_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 748 ipa_smp2p_out: ipa-ap-to-modem { 749 qcom,entry-name = "ipa"; 750 #qcom,smem-state-cells = <1>; 751 }; 752 753 ipa_smp2p_in: ipa-modem-to-ap { 754 qcom,entry-name = "ipa"; 755 interrupt-controller; 756 #interrupt-cells = <2>; 757 }; 758 }; 759 760 soc: soc@0 { 761 compatible = "simple-bus"; 762 ranges = <0 0 0 0 0x10 0>; 763 dma-ranges = <0 0 0 0 0x10 0>; 764 765 #address-cells = <2>; 766 #size-cells = <2>; 767 768 gcc: clock-controller@100000 { 769 compatible = "qcom,sm8550-gcc"; 770 reg = <0 0x00100000 0 0x1f4200>; 771 #clock-cells = <1>; 772 #reset-cells = <1>; 773 #power-domain-cells = <1>; 774 clocks = <&bi_tcxo_div2>, <&sleep_clk>, 775 <&pcie0_phy>, 776 <&pcie1_phy>, 777 <&pcie_1_phy_aux_clk>, 778 <&ufs_mem_phy 0>, 779 <&ufs_mem_phy 1>, 780 <&ufs_mem_phy 2>, 781 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 782 }; 783 784 ipcc: mailbox@408000 { 785 compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; 786 reg = <0 0x00408000 0 0x1000>; 787 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 788 interrupt-controller; 789 #interrupt-cells = <3>; 790 #mbox-cells = <2>; 791 }; 792 793 gpi_dma2: dma-controller@800000 { 794 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 795 #dma-cells = <3>; 796 reg = <0 0x00800000 0 0x60000>; 797 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 808 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 809 dma-channels = <12>; 810 dma-channel-mask = <0x3e>; 811 iommus = <&apps_smmu 0x436 0>; 812 status = "disabled"; 813 }; 814 815 qupv3_id_1: geniqup@8c0000 { 816 compatible = "qcom,geni-se-qup"; 817 reg = <0 0x008c0000 0 0x2000>; 818 ranges; 819 clock-names = "m-ahb", "s-ahb"; 820 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 821 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 822 iommus = <&apps_smmu 0x423 0>; 823 #address-cells = <2>; 824 #size-cells = <2>; 825 status = "disabled"; 826 827 i2c8: i2c@880000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x00880000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c8_data_clk>; 834 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 839 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 840 interconnect-names = "qup-core", "qup-config", "qup-memory"; 841 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 842 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 843 dma-names = "tx", "rx"; 844 status = "disabled"; 845 }; 846 847 spi8: spi@880000 { 848 compatible = "qcom,geni-spi"; 849 reg = <0 0x00880000 0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 852 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 855 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 856 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 857 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 858 interconnect-names = "qup-core", "qup-config", "qup-memory"; 859 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 860 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 861 dma-names = "tx", "rx"; 862 #address-cells = <1>; 863 #size-cells = <0>; 864 status = "disabled"; 865 }; 866 867 i2c9: i2c@884000 { 868 compatible = "qcom,geni-i2c"; 869 reg = <0 0x00884000 0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&qup_i2c9_data_clk>; 874 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 879 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 880 interconnect-names = "qup-core", "qup-config", "qup-memory"; 881 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 882 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 883 dma-names = "tx", "rx"; 884 status = "disabled"; 885 }; 886 887 spi9: spi@884000 { 888 compatible = "qcom,geni-spi"; 889 reg = <0 0x00884000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 892 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 895 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 897 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 898 interconnect-names = "qup-core", "qup-config", "qup-memory"; 899 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 900 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 901 dma-names = "tx", "rx"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 status = "disabled"; 905 }; 906 907 i2c10: i2c@888000 { 908 compatible = "qcom,geni-i2c"; 909 reg = <0 0x00888000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_i2c10_data_clk>; 914 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 919 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 920 interconnect-names = "qup-core", "qup-config", "qup-memory"; 921 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 922 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 923 dma-names = "tx", "rx"; 924 status = "disabled"; 925 }; 926 927 spi10: spi@888000 { 928 compatible = "qcom,geni-spi"; 929 reg = <0 0x00888000 0 0x4000>; 930 clock-names = "se"; 931 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 932 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 940 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 941 dma-names = "tx", "rx"; 942 #address-cells = <1>; 943 #size-cells = <0>; 944 status = "disabled"; 945 }; 946 947 i2c11: i2c@88c000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0 0x0088c000 0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_i2c11_data_clk>; 954 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 959 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 960 interconnect-names = "qup-core", "qup-config", "qup-memory"; 961 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 962 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 963 dma-names = "tx", "rx"; 964 status = "disabled"; 965 }; 966 967 spi11: spi@88c000 { 968 compatible = "qcom,geni-spi"; 969 reg = <0 0x0088c000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 972 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 975 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 976 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 977 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 978 interconnect-names = "qup-core", "qup-config", "qup-memory"; 979 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 980 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 981 dma-names = "tx", "rx"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 i2c12: i2c@890000 { 988 compatible = "qcom,geni-i2c"; 989 reg = <0 0x00890000 0 0x4000>; 990 clock-names = "se"; 991 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 992 pinctrl-names = "default"; 993 pinctrl-0 = <&qup_i2c12_data_clk>; 994 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 998 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 999 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1000 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1001 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1002 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1003 dma-names = "tx", "rx"; 1004 status = "disabled"; 1005 }; 1006 1007 spi12: spi@890000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0 0x00890000 0 0x4000>; 1010 clock-names = "se"; 1011 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1012 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1016 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1017 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1018 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1019 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1020 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1021 dma-names = "tx", "rx"; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 i2c13: i2c@894000 { 1028 compatible = "qcom,geni-i2c"; 1029 reg = <0 0x00894000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_i2c13_data_clk>; 1034 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1039 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1040 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1041 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1042 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1043 dma-names = "tx", "rx"; 1044 status = "disabled"; 1045 }; 1046 1047 spi13: spi@894000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0 0x00894000 0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1052 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1053 pinctrl-names = "default"; 1054 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1055 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1056 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1057 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1058 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1059 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1060 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1061 dma-names = "tx", "rx"; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c15: i2c@89c000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x0089c000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_i2c15_data_clk>; 1074 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1079 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1080 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1081 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1082 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1083 dma-names = "tx", "rx"; 1084 status = "disabled"; 1085 }; 1086 1087 spi15: spi@89c000 { 1088 compatible = "qcom,geni-spi"; 1089 reg = <0 0x0089c000 0 0x4000>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1092 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1093 pinctrl-names = "default"; 1094 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1095 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1097 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1098 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1099 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1100 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1101 dma-names = "tx", "rx"; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 status = "disabled"; 1105 }; 1106 }; 1107 1108 i2c_master_hub_0: geniqup@9c0000 { 1109 compatible = "qcom,geni-se-i2c-master-hub"; 1110 reg = <0x0 0x009c0000 0x0 0x2000>; 1111 clock-names = "s-ahb"; 1112 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1113 #address-cells = <2>; 1114 #size-cells = <2>; 1115 ranges; 1116 status = "disabled"; 1117 1118 i2c_hub_0: i2c@980000 { 1119 compatible = "qcom,geni-i2c-master-hub"; 1120 reg = <0x0 0x00980000 0x0 0x4000>; 1121 clock-names = "se", "core"; 1122 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1123 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&hub_i2c0_data_clk>; 1126 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1131 interconnect-names = "qup-core", "qup-config"; 1132 status = "disabled"; 1133 }; 1134 1135 i2c_hub_1: i2c@984000 { 1136 compatible = "qcom,geni-i2c-master-hub"; 1137 reg = <0x0 0x00984000 0x0 0x4000>; 1138 clock-names = "se", "core"; 1139 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1140 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&hub_i2c1_data_clk>; 1143 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1148 interconnect-names = "qup-core", "qup-config"; 1149 status = "disabled"; 1150 }; 1151 1152 i2c_hub_2: i2c@988000 { 1153 compatible = "qcom,geni-i2c-master-hub"; 1154 reg = <0x0 0x00988000 0x0 0x4000>; 1155 clock-names = "se", "core"; 1156 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1157 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1158 pinctrl-names = "default"; 1159 pinctrl-0 = <&hub_i2c2_data_clk>; 1160 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1165 interconnect-names = "qup-core", "qup-config"; 1166 status = "disabled"; 1167 }; 1168 1169 i2c_hub_3: i2c@98c000 { 1170 compatible = "qcom,geni-i2c-master-hub"; 1171 reg = <0x0 0x0098c000 0x0 0x4000>; 1172 clock-names = "se", "core"; 1173 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1174 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&hub_i2c3_data_clk>; 1177 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1181 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1182 interconnect-names = "qup-core", "qup-config"; 1183 status = "disabled"; 1184 }; 1185 1186 i2c_hub_4: i2c@990000 { 1187 compatible = "qcom,geni-i2c-master-hub"; 1188 reg = <0x0 0x00990000 0x0 0x4000>; 1189 clock-names = "se", "core"; 1190 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1191 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&hub_i2c4_data_clk>; 1194 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1199 interconnect-names = "qup-core", "qup-config"; 1200 status = "disabled"; 1201 }; 1202 1203 i2c_hub_5: i2c@994000 { 1204 compatible = "qcom,geni-i2c-master-hub"; 1205 reg = <0 0x00994000 0 0x4000>; 1206 clock-names = "se", "core"; 1207 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1208 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&hub_i2c5_data_clk>; 1211 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1216 interconnect-names = "qup-core", "qup-config"; 1217 status = "disabled"; 1218 }; 1219 1220 i2c_hub_6: i2c@998000 { 1221 compatible = "qcom,geni-i2c-master-hub"; 1222 reg = <0 0x00998000 0 0x4000>; 1223 clock-names = "se", "core"; 1224 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1225 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&hub_i2c6_data_clk>; 1228 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1232 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1233 interconnect-names = "qup-core", "qup-config"; 1234 status = "disabled"; 1235 }; 1236 1237 i2c_hub_7: i2c@99c000 { 1238 compatible = "qcom,geni-i2c-master-hub"; 1239 reg = <0 0x0099c000 0 0x4000>; 1240 clock-names = "se", "core"; 1241 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1242 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&hub_i2c7_data_clk>; 1245 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1249 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1250 interconnect-names = "qup-core", "qup-config"; 1251 status = "disabled"; 1252 }; 1253 1254 i2c_hub_8: i2c@9a0000 { 1255 compatible = "qcom,geni-i2c-master-hub"; 1256 reg = <0 0x009a0000 0 0x4000>; 1257 clock-names = "se", "core"; 1258 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1259 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&hub_i2c8_data_clk>; 1262 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1263 #address-cells = <1>; 1264 #size-cells = <0>; 1265 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1266 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1267 interconnect-names = "qup-core", "qup-config"; 1268 status = "disabled"; 1269 }; 1270 1271 i2c_hub_9: i2c@9a4000 { 1272 compatible = "qcom,geni-i2c-master-hub"; 1273 reg = <0 0x009a4000 0 0x4000>; 1274 clock-names = "se", "core"; 1275 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1276 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&hub_i2c9_data_clk>; 1279 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1283 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; 1284 interconnect-names = "qup-core", "qup-config"; 1285 status = "disabled"; 1286 }; 1287 }; 1288 1289 gpi_dma1: dma-controller@a00000 { 1290 compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; 1291 #dma-cells = <3>; 1292 reg = <0 0x00a00000 0 0x60000>; 1293 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1305 dma-channels = <12>; 1306 dma-channel-mask = <0x1e>; 1307 iommus = <&apps_smmu 0xb6 0>; 1308 status = "disabled"; 1309 }; 1310 1311 qupv3_id_0: geniqup@ac0000 { 1312 compatible = "qcom,geni-se-qup"; 1313 reg = <0 0x00ac0000 0 0x2000>; 1314 ranges; 1315 clock-names = "m-ahb", "s-ahb"; 1316 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1317 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1318 iommus = <&apps_smmu 0xa3 0>; 1319 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1320 interconnect-names = "qup-core"; 1321 #address-cells = <2>; 1322 #size-cells = <2>; 1323 status = "disabled"; 1324 1325 i2c0: i2c@a80000 { 1326 compatible = "qcom,geni-i2c"; 1327 reg = <0 0x00a80000 0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_i2c0_data_clk>; 1332 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1336 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1337 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1338 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1339 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1340 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1341 dma-names = "tx", "rx"; 1342 status = "disabled"; 1343 }; 1344 1345 spi0: spi@a80000 { 1346 compatible = "qcom,geni-spi"; 1347 reg = <0 0x00a80000 0 0x4000>; 1348 clock-names = "se"; 1349 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1350 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1353 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1354 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1355 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1356 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1357 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1358 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1359 dma-names = "tx", "rx"; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 i2c1: i2c@a84000 { 1366 compatible = "qcom,geni-i2c"; 1367 reg = <0 0x00a84000 0 0x4000>; 1368 clock-names = "se"; 1369 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1370 pinctrl-names = "default"; 1371 pinctrl-0 = <&qup_i2c1_data_clk>; 1372 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1376 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1377 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1378 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1379 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1380 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1381 dma-names = "tx", "rx"; 1382 status = "disabled"; 1383 }; 1384 1385 spi1: spi@a84000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00a84000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1390 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1391 pinctrl-names = "default"; 1392 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1394 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1395 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1396 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1397 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1398 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 i2c2: i2c@a88000 { 1406 compatible = "qcom,geni-i2c"; 1407 reg = <0 0x00a88000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&qup_i2c2_data_clk>; 1412 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1417 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1418 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1419 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1420 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1421 dma-names = "tx", "rx"; 1422 status = "disabled"; 1423 }; 1424 1425 spi2: spi@a88000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00a88000 0 0x4000>; 1428 clock-names = "se"; 1429 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1430 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1431 pinctrl-names = "default"; 1432 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1435 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1436 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1437 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1438 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1439 dma-names = "tx", "rx"; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 status = "disabled"; 1443 }; 1444 1445 i2c3: i2c@a8c000 { 1446 compatible = "qcom,geni-i2c"; 1447 reg = <0 0x00a8c000 0 0x4000>; 1448 clock-names = "se"; 1449 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&qup_i2c3_data_clk>; 1452 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1456 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1457 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1458 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1459 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1460 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1461 dma-names = "tx", "rx"; 1462 status = "disabled"; 1463 }; 1464 1465 spi3: spi@a8c000 { 1466 compatible = "qcom,geni-spi"; 1467 reg = <0 0x00a8c000 0 0x4000>; 1468 clock-names = "se"; 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1470 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1475 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1478 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1479 dma-names = "tx", "rx"; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 status = "disabled"; 1483 }; 1484 1485 i2c4: i2c@a90000 { 1486 compatible = "qcom,geni-i2c"; 1487 reg = <0 0x00a90000 0 0x4000>; 1488 clock-names = "se"; 1489 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1490 pinctrl-names = "default"; 1491 pinctrl-0 = <&qup_i2c4_data_clk>; 1492 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1497 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1500 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1501 dma-names = "tx", "rx"; 1502 status = "disabled"; 1503 }; 1504 1505 spi4: spi@a90000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0 0x00a90000 0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1510 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1513 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1514 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1515 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1516 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1517 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1518 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1519 dma-names = "tx", "rx"; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 status = "disabled"; 1523 }; 1524 1525 i2c5: i2c@a94000 { 1526 compatible = "qcom,geni-i2c"; 1527 reg = <0 0x00a94000 0 0x4000>; 1528 clock-names = "se"; 1529 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1530 pinctrl-names = "default"; 1531 pinctrl-0 = <&qup_i2c5_data_clk>; 1532 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1533 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1534 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1535 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1536 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1537 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1538 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1539 dma-names = "tx", "rx"; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 }; 1544 1545 spi5: spi@a94000 { 1546 compatible = "qcom,geni-spi"; 1547 reg = <0 0x00a94000 0 0x4000>; 1548 clock-names = "se"; 1549 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1550 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1551 pinctrl-names = "default"; 1552 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1555 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1556 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1557 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1558 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1559 dma-names = "tx", "rx"; 1560 #address-cells = <1>; 1561 #size-cells = <0>; 1562 status = "disabled"; 1563 }; 1564 1565 i2c6: i2c@a98000 { 1566 compatible = "qcom,geni-i2c"; 1567 reg = <0 0x00a98000 0 0x4000>; 1568 clock-names = "se"; 1569 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1570 pinctrl-names = "default"; 1571 pinctrl-0 = <&qup_i2c6_data_clk>; 1572 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1573 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1574 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1575 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1576 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1577 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1578 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1579 dma-names = "tx", "rx"; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 status = "disabled"; 1583 }; 1584 1585 spi6: spi@a98000 { 1586 compatible = "qcom,geni-spi"; 1587 reg = <0 0x00a98000 0 0x4000>; 1588 clock-names = "se"; 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1590 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1591 pinctrl-names = "default"; 1592 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1594 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1595 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1596 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1597 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1598 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1599 dma-names = "tx", "rx"; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 status = "disabled"; 1603 }; 1604 1605 uart7: serial@a9c000 { 1606 compatible = "qcom,geni-debug-uart"; 1607 reg = <0 0x00a9c000 0 0x4000>; 1608 clock-names = "se"; 1609 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1610 pinctrl-names = "default"; 1611 pinctrl-0 = <&qup_uart7_default>; 1612 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1613 interconnect-names = "qup-core", "qup-config"; 1614 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1615 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1616 status = "disabled"; 1617 }; 1618 }; 1619 1620 cnoc_main: interconnect@1500000 { 1621 compatible = "qcom,sm8550-cnoc-main"; 1622 reg = <0 0x01500000 0 0x13080>; 1623 #interconnect-cells = <2>; 1624 qcom,bcm-voters = <&apps_bcm_voter>; 1625 }; 1626 1627 config_noc: interconnect@1600000 { 1628 compatible = "qcom,sm8550-config-noc"; 1629 reg = <0 0x01600000 0 0x6200>; 1630 #interconnect-cells = <2>; 1631 qcom,bcm-voters = <&apps_bcm_voter>; 1632 }; 1633 1634 system_noc: interconnect@1680000 { 1635 compatible = "qcom,sm8550-system-noc"; 1636 reg = <0 0x01680000 0 0x1d080>; 1637 #interconnect-cells = <2>; 1638 qcom,bcm-voters = <&apps_bcm_voter>; 1639 }; 1640 1641 pcie_noc: interconnect@16c0000 { 1642 compatible = "qcom,sm8550-pcie-anoc"; 1643 reg = <0 0x016c0000 0 0x12200>; 1644 #interconnect-cells = <2>; 1645 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1646 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1647 qcom,bcm-voters = <&apps_bcm_voter>; 1648 }; 1649 1650 aggre1_noc: interconnect@16e0000 { 1651 compatible = "qcom,sm8550-aggre1-noc"; 1652 reg = <0 0x016e0000 0 0x14400>; 1653 #interconnect-cells = <2>; 1654 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1655 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1656 qcom,bcm-voters = <&apps_bcm_voter>; 1657 }; 1658 1659 aggre2_noc: interconnect@1700000 { 1660 compatible = "qcom,sm8550-aggre2-noc"; 1661 reg = <0 0x01700000 0 0x1e400>; 1662 #interconnect-cells = <2>; 1663 clocks = <&rpmhcc RPMH_IPA_CLK>; 1664 qcom,bcm-voters = <&apps_bcm_voter>; 1665 }; 1666 1667 mmss_noc: interconnect@1780000 { 1668 compatible = "qcom,sm8550-mmss-noc"; 1669 reg = <0 0x01780000 0 0x5b800>; 1670 #interconnect-cells = <2>; 1671 qcom,bcm-voters = <&apps_bcm_voter>; 1672 }; 1673 1674 pcie0: pci@1c00000 { 1675 device_type = "pci"; 1676 compatible = "qcom,pcie-sm8550"; 1677 reg = <0 0x01c00000 0 0x3000>, 1678 <0 0x60000000 0 0xf1d>, 1679 <0 0x60000f20 0 0xa8>, 1680 <0 0x60001000 0 0x1000>, 1681 <0 0x60100000 0 0x100000>; 1682 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1683 #address-cells = <3>; 1684 #size-cells = <2>; 1685 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1686 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1687 bus-range = <0x00 0xff>; 1688 1689 dma-coherent; 1690 1691 linux,pci-domain = <0>; 1692 num-lanes = <2>; 1693 1694 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1695 interrupt-names = "msi"; 1696 1697 #interrupt-cells = <1>; 1698 interrupt-map-mask = <0 0 0 0x7>; 1699 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1700 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1701 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1702 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1703 1704 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1705 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1706 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1707 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1708 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1709 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1710 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; 1711 clock-names = "aux", 1712 "cfg", 1713 "bus_master", 1714 "bus_slave", 1715 "slave_q2a", 1716 "ddrss_sf_tbu", 1717 "noc_aggr"; 1718 1719 interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 1720 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; 1721 interconnect-names = "pcie-mem", "cpu-pcie"; 1722 1723 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 1724 <0x100 &apps_smmu 0x1401 0x1>; 1725 1726 resets = <&gcc GCC_PCIE_0_BCR>; 1727 reset-names = "pci"; 1728 1729 power-domains = <&gcc PCIE_0_GDSC>; 1730 1731 phys = <&pcie0_phy>; 1732 phy-names = "pciephy"; 1733 1734 status = "disabled"; 1735 }; 1736 1737 pcie0_phy: phy@1c06000 { 1738 compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; 1739 reg = <0 0x01c06000 0 0x2000>; 1740 1741 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1742 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1743 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1744 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1745 <&gcc GCC_PCIE_0_PIPE_CLK>; 1746 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1747 "pipe"; 1748 1749 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1750 reset-names = "phy"; 1751 1752 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1753 assigned-clock-rates = <100000000>; 1754 1755 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1756 1757 #clock-cells = <0>; 1758 clock-output-names = "pcie0_pipe_clk"; 1759 1760 #phy-cells = <0>; 1761 1762 status = "disabled"; 1763 }; 1764 1765 pcie1: pci@1c08000 { 1766 device_type = "pci"; 1767 compatible = "qcom,pcie-sm8550"; 1768 reg = <0x0 0x01c08000 0x0 0x3000>, 1769 <0x0 0x40000000 0x0 0xf1d>, 1770 <0x0 0x40000f20 0x0 0xa8>, 1771 <0x0 0x40001000 0x0 0x1000>, 1772 <0x0 0x40100000 0x0 0x100000>; 1773 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1774 #address-cells = <3>; 1775 #size-cells = <2>; 1776 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1777 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1778 bus-range = <0x00 0xff>; 1779 1780 dma-coherent; 1781 1782 linux,pci-domain = <1>; 1783 num-lanes = <2>; 1784 1785 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1786 interrupt-names = "msi"; 1787 1788 #interrupt-cells = <1>; 1789 interrupt-map-mask = <0 0 0 0x7>; 1790 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1791 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1792 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1793 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1794 1795 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1796 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1797 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1798 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1799 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1800 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 1801 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1802 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 1803 clock-names = "aux", 1804 "cfg", 1805 "bus_master", 1806 "bus_slave", 1807 "slave_q2a", 1808 "ddrss_sf_tbu", 1809 "noc_aggr", 1810 "cnoc_sf_axi"; 1811 1812 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1813 assigned-clock-rates = <19200000>; 1814 1815 interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 1816 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; 1817 interconnect-names = "pcie-mem", "cpu-pcie"; 1818 1819 iommu-map = <0x0 &apps_smmu 0x1480 0x1>, 1820 <0x100 &apps_smmu 0x1481 0x1>; 1821 1822 resets = <&gcc GCC_PCIE_1_BCR>, 1823 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1824 reset-names = "pci", "link_down"; 1825 1826 power-domains = <&gcc PCIE_1_GDSC>; 1827 1828 phys = <&pcie1_phy>; 1829 phy-names = "pciephy"; 1830 1831 status = "disabled"; 1832 }; 1833 1834 pcie1_phy: phy@1c0e000 { 1835 compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; 1836 reg = <0x0 0x01c0e000 0x0 0x2000>; 1837 1838 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1839 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1840 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1841 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1842 <&gcc GCC_PCIE_1_PIPE_CLK>; 1843 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1844 "pipe"; 1845 1846 resets = <&gcc GCC_PCIE_1_PHY_BCR>, 1847 <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; 1848 reset-names = "phy", "phy_nocsr"; 1849 1850 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1851 assigned-clock-rates = <100000000>; 1852 1853 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1854 1855 #clock-cells = <0>; 1856 clock-output-names = "pcie1_pipe_clk"; 1857 1858 #phy-cells = <0>; 1859 1860 status = "disabled"; 1861 }; 1862 1863 cryptobam: dma-controller@1dc4000 { 1864 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1865 reg = <0x0 0x01dc4000 0x0 0x28000>; 1866 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1867 #dma-cells = <1>; 1868 qcom,ee = <0>; 1869 qcom,controlled-remotely; 1870 iommus = <&apps_smmu 0x480 0x0>, 1871 <&apps_smmu 0x481 0x0>; 1872 }; 1873 1874 crypto: crypto@1dfa000 { 1875 compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce"; 1876 reg = <0x0 0x01dfa000 0x0 0x6000>; 1877 dmas = <&cryptobam 4>, <&cryptobam 5>; 1878 dma-names = "rx", "tx"; 1879 iommus = <&apps_smmu 0x480 0x0>, 1880 <&apps_smmu 0x481 0x0>; 1881 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1882 interconnect-names = "memory"; 1883 }; 1884 1885 ufs_mem_phy: phy@1d80000 { 1886 compatible = "qcom,sm8550-qmp-ufs-phy"; 1887 reg = <0x0 0x01d80000 0x0 0x2000>; 1888 clocks = <&tcsr TCSR_UFS_CLKREF_EN>, 1889 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1890 clock-names = "ref", "ref_aux"; 1891 1892 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1893 1894 resets = <&ufs_mem_hc 0>; 1895 reset-names = "ufsphy"; 1896 1897 #clock-cells = <1>; 1898 #phy-cells = <0>; 1899 1900 status = "disabled"; 1901 }; 1902 1903 ufs_mem_hc: ufs@1d84000 { 1904 compatible = "qcom,sm8550-ufshc", "qcom,ufshc", 1905 "jedec,ufs-2.0"; 1906 reg = <0x0 0x01d84000 0x0 0x3000>; 1907 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1908 phys = <&ufs_mem_phy>; 1909 phy-names = "ufsphy"; 1910 lanes-per-direction = <2>; 1911 #reset-cells = <1>; 1912 resets = <&gcc GCC_UFS_PHY_BCR>; 1913 reset-names = "rst"; 1914 1915 power-domains = <&gcc UFS_PHY_GDSC>; 1916 required-opps = <&rpmhpd_opp_nom>; 1917 1918 iommus = <&apps_smmu 0x60 0x0>; 1919 dma-coherent; 1920 1921 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 1922 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 1923 1924 interconnect-names = "ufs-ddr", "cpu-ufs"; 1925 clock-names = "core_clk", 1926 "bus_aggr_clk", 1927 "iface_clk", 1928 "core_clk_unipro", 1929 "ref_clk", 1930 "tx_lane0_sync_clk", 1931 "rx_lane0_sync_clk", 1932 "rx_lane1_sync_clk"; 1933 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1934 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1935 <&gcc GCC_UFS_PHY_AHB_CLK>, 1936 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1937 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1938 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1939 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1940 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1941 freq-table-hz = 1942 <75000000 300000000>, 1943 <0 0>, 1944 <0 0>, 1945 <75000000 300000000>, 1946 <100000000 403000000>, 1947 <0 0>, 1948 <0 0>, 1949 <0 0>; 1950 qcom,ice = <&ice>; 1951 1952 status = "disabled"; 1953 }; 1954 1955 ice: crypto@1d88000 { 1956 compatible = "qcom,sm8550-inline-crypto-engine", 1957 "qcom,inline-crypto-engine"; 1958 reg = <0 0x01d88000 0 0x8000>; 1959 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1960 }; 1961 1962 tcsr_mutex: hwlock@1f40000 { 1963 compatible = "qcom,tcsr-mutex"; 1964 reg = <0 0x01f40000 0 0x20000>; 1965 #hwlock-cells = <1>; 1966 }; 1967 1968 tcsr: clock-controller@1fc0000 { 1969 compatible = "qcom,sm8550-tcsr", "syscon"; 1970 reg = <0 0x01fc0000 0 0x30000>; 1971 clocks = <&rpmhcc RPMH_CXO_CLK>; 1972 #clock-cells = <1>; 1973 #reset-cells = <1>; 1974 }; 1975 1976 gpucc: clock-controller@3d90000 { 1977 compatible = "qcom,sm8550-gpucc"; 1978 reg = <0 0x03d90000 0 0xa000>; 1979 clocks = <&bi_tcxo_div2>, 1980 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1981 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1982 #clock-cells = <1>; 1983 #reset-cells = <1>; 1984 #power-domain-cells = <1>; 1985 }; 1986 1987 remoteproc_mpss: remoteproc@4080000 { 1988 compatible = "qcom,sm8550-mpss-pas"; 1989 reg = <0x0 0x04080000 0x0 0x10000>; 1990 1991 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 1992 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1993 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1994 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1995 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1996 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1997 interrupt-names = "wdog", "fatal", "ready", "handover", 1998 "stop-ack", "shutdown-ack"; 1999 2000 clocks = <&rpmhcc RPMH_CXO_CLK>; 2001 clock-names = "xo"; 2002 2003 power-domains = <&rpmhpd RPMHPD_CX>, 2004 <&rpmhpd RPMHPD_MSS>; 2005 power-domain-names = "cx", "mss"; 2006 2007 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2008 2009 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; 2010 2011 qcom,qmp = <&aoss_qmp>; 2012 2013 qcom,smem-states = <&smp2p_modem_out 0>; 2014 qcom,smem-state-names = "stop"; 2015 2016 status = "disabled"; 2017 2018 glink-edge { 2019 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2020 IPCC_MPROC_SIGNAL_GLINK_QMP 2021 IRQ_TYPE_EDGE_RISING>; 2022 mboxes = <&ipcc IPCC_CLIENT_MPSS 2023 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2024 label = "mpss"; 2025 qcom,remote-pid = <1>; 2026 }; 2027 }; 2028 2029 remoteproc_adsp: remoteproc@6800000 { 2030 compatible = "qcom,sm8550-adsp-pas"; 2031 reg = <0x0 0x06800000 0x0 0x10000>; 2032 2033 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2034 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2035 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2036 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2037 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2038 interrupt-names = "wdog", "fatal", "ready", 2039 "handover", "stop-ack"; 2040 2041 clocks = <&rpmhcc RPMH_CXO_CLK>; 2042 clock-names = "xo"; 2043 2044 power-domains = <&rpmhpd RPMHPD_LCX>, 2045 <&rpmhpd RPMHPD_LMX>; 2046 power-domain-names = "lcx", "lmx"; 2047 2048 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 2049 2050 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2051 2052 qcom,qmp = <&aoss_qmp>; 2053 2054 qcom,smem-states = <&smp2p_adsp_out 0>; 2055 qcom,smem-state-names = "stop"; 2056 2057 status = "disabled"; 2058 2059 remoteproc_adsp_glink: glink-edge { 2060 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2061 IPCC_MPROC_SIGNAL_GLINK_QMP 2062 IRQ_TYPE_EDGE_RISING>; 2063 mboxes = <&ipcc IPCC_CLIENT_LPASS 2064 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2065 2066 label = "lpass"; 2067 qcom,remote-pid = <2>; 2068 2069 fastrpc { 2070 compatible = "qcom,fastrpc"; 2071 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2072 label = "adsp"; 2073 qcom,non-secure-domain; 2074 #address-cells = <1>; 2075 #size-cells = <0>; 2076 2077 compute-cb@3 { 2078 compatible = "qcom,fastrpc-compute-cb"; 2079 reg = <3>; 2080 iommus = <&apps_smmu 0x1003 0x80>, 2081 <&apps_smmu 0x1063 0x0>; 2082 dma-coherent; 2083 }; 2084 2085 compute-cb@4 { 2086 compatible = "qcom,fastrpc-compute-cb"; 2087 reg = <4>; 2088 iommus = <&apps_smmu 0x1004 0x80>, 2089 <&apps_smmu 0x1064 0x0>; 2090 dma-coherent; 2091 }; 2092 2093 compute-cb@5 { 2094 compatible = "qcom,fastrpc-compute-cb"; 2095 reg = <5>; 2096 iommus = <&apps_smmu 0x1005 0x80>, 2097 <&apps_smmu 0x1065 0x0>; 2098 dma-coherent; 2099 }; 2100 2101 compute-cb@6 { 2102 compatible = "qcom,fastrpc-compute-cb"; 2103 reg = <6>; 2104 iommus = <&apps_smmu 0x1006 0x80>, 2105 <&apps_smmu 0x1066 0x0>; 2106 dma-coherent; 2107 }; 2108 2109 compute-cb@7 { 2110 compatible = "qcom,fastrpc-compute-cb"; 2111 reg = <7>; 2112 iommus = <&apps_smmu 0x1007 0x80>, 2113 <&apps_smmu 0x1067 0x0>; 2114 dma-coherent; 2115 }; 2116 }; 2117 2118 gpr { 2119 compatible = "qcom,gpr"; 2120 qcom,glink-channels = "adsp_apps"; 2121 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2122 qcom,intents = <512 20>; 2123 #address-cells = <1>; 2124 #size-cells = <0>; 2125 2126 q6apm: service@1 { 2127 compatible = "qcom,q6apm"; 2128 reg = <GPR_APM_MODULE_IID>; 2129 #sound-dai-cells = <0>; 2130 qcom,protection-domain = "avs/audio", 2131 "msm/adsp/audio_pd"; 2132 2133 q6apmdai: dais { 2134 compatible = "qcom,q6apm-dais"; 2135 iommus = <&apps_smmu 0x1001 0x80>, 2136 <&apps_smmu 0x1061 0x0>; 2137 }; 2138 2139 q6apmbedai: bedais { 2140 compatible = "qcom,q6apm-lpass-dais"; 2141 #sound-dai-cells = <1>; 2142 }; 2143 }; 2144 2145 q6prm: service@2 { 2146 compatible = "qcom,q6prm"; 2147 reg = <GPR_PRM_MODULE_IID>; 2148 qcom,protection-domain = "avs/audio", 2149 "msm/adsp/audio_pd"; 2150 2151 q6prmcc: clock-controller { 2152 compatible = "qcom,q6prm-lpass-clocks"; 2153 #clock-cells = <2>; 2154 }; 2155 }; 2156 }; 2157 }; 2158 }; 2159 2160 lpass_wsa2macro: codec@6aa0000 { 2161 compatible = "qcom,sm8550-lpass-wsa-macro"; 2162 reg = <0 0x06aa0000 0 0x1000>; 2163 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2164 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2165 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2166 <&lpass_vamacro>; 2167 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2168 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2169 assigned-clock-rates = <19200000>; 2170 2171 #clock-cells = <0>; 2172 clock-output-names = "wsa2-mclk"; 2173 pinctrl-names = "default"; 2174 pinctrl-0 = <&wsa2_swr_active>; 2175 #sound-dai-cells = <1>; 2176 }; 2177 2178 swr3: soundwire@6ab0000 { 2179 compatible = "qcom,soundwire-v2.0.0"; 2180 reg = <0 0x06ab0000 0 0x10000>; 2181 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2182 clocks = <&lpass_wsa2macro>; 2183 clock-names = "iface"; 2184 label = "WSA2"; 2185 2186 qcom,din-ports = <4>; 2187 qcom,dout-ports = <9>; 2188 2189 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2190 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2191 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2192 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2193 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2194 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2195 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2196 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2197 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2198 2199 #address-cells = <2>; 2200 #size-cells = <0>; 2201 #sound-dai-cells = <1>; 2202 status = "disabled"; 2203 }; 2204 2205 lpass_rxmacro: codec@6ac0000 { 2206 compatible = "qcom,sm8550-lpass-rx-macro"; 2207 reg = <0 0x06ac0000 0 0x1000>; 2208 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2209 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2210 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2211 <&lpass_vamacro>; 2212 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2213 2214 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2215 assigned-clock-rates = <19200000>; 2216 2217 #clock-cells = <0>; 2218 clock-output-names = "mclk"; 2219 pinctrl-names = "default"; 2220 pinctrl-0 = <&rx_swr_active>; 2221 #sound-dai-cells = <1>; 2222 }; 2223 2224 swr1: soundwire@6ad0000 { 2225 compatible = "qcom,soundwire-v2.0.0"; 2226 reg = <0 0x06ad0000 0 0x10000>; 2227 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&lpass_rxmacro>; 2229 clock-names = "iface"; 2230 label = "RX"; 2231 2232 qcom,din-ports = <0>; 2233 qcom,dout-ports = <10>; 2234 2235 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; 2236 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; 2237 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2238 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2239 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; 2240 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; 2241 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; 2242 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2243 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; 2244 2245 #address-cells = <2>; 2246 #size-cells = <0>; 2247 #sound-dai-cells = <1>; 2248 status = "disabled"; 2249 }; 2250 2251 lpass_txmacro: codec@6ae0000 { 2252 compatible = "qcom,sm8550-lpass-tx-macro"; 2253 reg = <0 0x06ae0000 0 0x1000>; 2254 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2255 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2256 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2257 <&lpass_vamacro>; 2258 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2259 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2260 2261 assigned-clock-rates = <19200000>; 2262 2263 #clock-cells = <0>; 2264 clock-output-names = "mclk"; 2265 pinctrl-names = "default"; 2266 pinctrl-0 = <&tx_swr_active>; 2267 #sound-dai-cells = <1>; 2268 }; 2269 2270 lpass_wsamacro: codec@6b00000 { 2271 compatible = "qcom,sm8550-lpass-wsa-macro"; 2272 reg = <0 0x06b00000 0 0x1000>; 2273 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2274 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2275 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2276 <&lpass_vamacro>; 2277 clock-names = "mclk", "macro", "dcodec", "fsgen"; 2278 2279 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2280 assigned-clock-rates = <19200000>; 2281 2282 #clock-cells = <0>; 2283 clock-output-names = "mclk"; 2284 pinctrl-names = "default"; 2285 pinctrl-0 = <&wsa_swr_active>; 2286 #sound-dai-cells = <1>; 2287 }; 2288 2289 swr0: soundwire@6b10000 { 2290 compatible = "qcom,soundwire-v2.0.0"; 2291 reg = <0 0x06b10000 0 0x10000>; 2292 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2293 clocks = <&lpass_wsamacro>; 2294 clock-names = "iface"; 2295 label = "WSA"; 2296 2297 qcom,din-ports = <4>; 2298 qcom,dout-ports = <9>; 2299 2300 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2301 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2302 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2303 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2304 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2305 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2306 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2307 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2308 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2309 2310 #address-cells = <2>; 2311 #size-cells = <0>; 2312 #sound-dai-cells = <1>; 2313 status = "disabled"; 2314 }; 2315 2316 swr2: soundwire@6d30000 { 2317 compatible = "qcom,soundwire-v2.0.0"; 2318 reg = <0 0x06d30000 0 0x10000>; 2319 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2320 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2321 interrupt-names = "core", "wakeup"; 2322 clocks = <&lpass_txmacro>; 2323 clock-names = "iface"; 2324 label = "TX"; 2325 2326 qcom,din-ports = <4>; 2327 qcom,dout-ports = <0>; 2328 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2329 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2330 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2331 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2332 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2333 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2334 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2335 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2336 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2337 2338 #address-cells = <2>; 2339 #size-cells = <0>; 2340 #sound-dai-cells = <1>; 2341 status = "disabled"; 2342 }; 2343 2344 lpass_vamacro: codec@6d44000 { 2345 compatible = "qcom,sm8550-lpass-va-macro"; 2346 reg = <0 0x06d44000 0 0x1000>; 2347 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2348 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2349 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2350 clock-names = "mclk", "macro", "dcodec"; 2351 2352 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2353 assigned-clock-rates = <19200000>; 2354 2355 #clock-cells = <0>; 2356 clock-output-names = "fsgen"; 2357 #sound-dai-cells = <1>; 2358 }; 2359 2360 lpass_tlmm: pinctrl@6e80000 { 2361 compatible = "qcom,sm8550-lpass-lpi-pinctrl"; 2362 reg = <0 0x06e80000 0 0x20000>, 2363 <0 0x07250000 0 0x10000>; 2364 gpio-controller; 2365 #gpio-cells = <2>; 2366 gpio-ranges = <&lpass_tlmm 0 0 23>; 2367 2368 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2369 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2370 clock-names = "core", "audio"; 2371 2372 tx_swr_active: tx-swr-active-state { 2373 clk-pins { 2374 pins = "gpio0"; 2375 function = "swr_tx_clk"; 2376 drive-strength = <2>; 2377 slew-rate = <1>; 2378 bias-disable; 2379 }; 2380 2381 data-pins { 2382 pins = "gpio1", "gpio2", "gpio14"; 2383 function = "swr_tx_data"; 2384 drive-strength = <2>; 2385 slew-rate = <1>; 2386 bias-bus-hold; 2387 }; 2388 }; 2389 2390 rx_swr_active: rx-swr-active-state { 2391 clk-pins { 2392 pins = "gpio3"; 2393 function = "swr_rx_clk"; 2394 drive-strength = <2>; 2395 slew-rate = <1>; 2396 bias-disable; 2397 }; 2398 2399 data-pins { 2400 pins = "gpio4", "gpio5"; 2401 function = "swr_rx_data"; 2402 drive-strength = <2>; 2403 slew-rate = <1>; 2404 bias-bus-hold; 2405 }; 2406 }; 2407 2408 dmic01_default: dmic01-default-state { 2409 clk-pins { 2410 pins = "gpio6"; 2411 function = "dmic1_clk"; 2412 drive-strength = <8>; 2413 output-high; 2414 }; 2415 2416 data-pins { 2417 pins = "gpio7"; 2418 function = "dmic1_data"; 2419 drive-strength = <8>; 2420 input-enable; 2421 }; 2422 }; 2423 2424 dmic02_default: dmic02-default-state { 2425 clk-pins { 2426 pins = "gpio8"; 2427 function = "dmic2_clk"; 2428 drive-strength = <8>; 2429 output-high; 2430 }; 2431 2432 data-pins { 2433 pins = "gpio9"; 2434 function = "dmic2_data"; 2435 drive-strength = <8>; 2436 input-enable; 2437 }; 2438 }; 2439 2440 wsa_swr_active: wsa-swr-active-state { 2441 clk-pins { 2442 pins = "gpio10"; 2443 function = "wsa_swr_clk"; 2444 drive-strength = <2>; 2445 slew-rate = <1>; 2446 bias-disable; 2447 }; 2448 2449 data-pins { 2450 pins = "gpio11"; 2451 function = "wsa_swr_data"; 2452 drive-strength = <2>; 2453 slew-rate = <1>; 2454 bias-bus-hold; 2455 }; 2456 }; 2457 2458 wsa2_swr_active: wsa2-swr-active-state { 2459 clk-pins { 2460 pins = "gpio15"; 2461 function = "wsa2_swr_clk"; 2462 drive-strength = <2>; 2463 slew-rate = <1>; 2464 bias-disable; 2465 }; 2466 2467 data-pins { 2468 pins = "gpio16"; 2469 function = "wsa2_swr_data"; 2470 drive-strength = <2>; 2471 slew-rate = <1>; 2472 bias-bus-hold; 2473 }; 2474 }; 2475 }; 2476 2477 lpass_lpiaon_noc: interconnect@7400000 { 2478 compatible = "qcom,sm8550-lpass-lpiaon-noc"; 2479 reg = <0 0x07400000 0 0x19080>; 2480 #interconnect-cells = <2>; 2481 qcom,bcm-voters = <&apps_bcm_voter>; 2482 }; 2483 2484 lpass_lpicx_noc: interconnect@7430000 { 2485 compatible = "qcom,sm8550-lpass-lpicx-noc"; 2486 reg = <0 0x07430000 0 0x3a200>; 2487 #interconnect-cells = <2>; 2488 qcom,bcm-voters = <&apps_bcm_voter>; 2489 }; 2490 2491 lpass_ag_noc: interconnect@7e40000 { 2492 compatible = "qcom,sm8550-lpass-ag-noc"; 2493 reg = <0 0x07e40000 0 0xe080>; 2494 #interconnect-cells = <2>; 2495 qcom,bcm-voters = <&apps_bcm_voter>; 2496 }; 2497 2498 sdhc_2: mmc@8804000 { 2499 compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; 2500 reg = <0 0x08804000 0 0x1000>; 2501 2502 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2504 interrupt-names = "hc_irq", "pwr_irq"; 2505 2506 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2507 <&gcc GCC_SDCC2_APPS_CLK>, 2508 <&rpmhcc RPMH_CXO_CLK>; 2509 clock-names = "iface", "core", "xo"; 2510 iommus = <&apps_smmu 0x540 0>; 2511 qcom,dll-config = <0x0007642c>; 2512 qcom,ddr-config = <0x80040868>; 2513 power-domains = <&rpmhpd RPMHPD_CX>; 2514 operating-points-v2 = <&sdhc2_opp_table>; 2515 2516 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2517 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2518 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 2519 bus-width = <4>; 2520 dma-coherent; 2521 2522 /* Forbid SDR104/SDR50 - broken hw! */ 2523 sdhci-caps-mask = <0x3 0>; 2524 2525 status = "disabled"; 2526 2527 sdhc2_opp_table: opp-table { 2528 compatible = "operating-points-v2"; 2529 2530 opp-19200000 { 2531 opp-hz = /bits/ 64 <19200000>; 2532 required-opps = <&rpmhpd_opp_min_svs>; 2533 }; 2534 2535 opp-50000000 { 2536 opp-hz = /bits/ 64 <50000000>; 2537 required-opps = <&rpmhpd_opp_low_svs>; 2538 }; 2539 2540 opp-100000000 { 2541 opp-hz = /bits/ 64 <100000000>; 2542 required-opps = <&rpmhpd_opp_svs>; 2543 }; 2544 2545 opp-202000000 { 2546 opp-hz = /bits/ 64 <202000000>; 2547 required-opps = <&rpmhpd_opp_svs_l1>; 2548 }; 2549 }; 2550 }; 2551 2552 videocc: clock-controller@aaf0000 { 2553 compatible = "qcom,sm8550-videocc"; 2554 reg = <0 0x0aaf0000 0 0x10000>; 2555 clocks = <&bi_tcxo_div2>, 2556 <&gcc GCC_VIDEO_AHB_CLK>; 2557 power-domains = <&rpmhpd RPMHPD_MMCX>; 2558 required-opps = <&rpmhpd_opp_low_svs>; 2559 #clock-cells = <1>; 2560 #reset-cells = <1>; 2561 #power-domain-cells = <1>; 2562 }; 2563 2564 mdss: display-subsystem@ae00000 { 2565 compatible = "qcom,sm8550-mdss"; 2566 reg = <0 0x0ae00000 0 0x1000>; 2567 reg-names = "mdss"; 2568 2569 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2570 interrupt-controller; 2571 #interrupt-cells = <1>; 2572 2573 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2574 <&gcc GCC_DISP_AHB_CLK>, 2575 <&gcc GCC_DISP_HF_AXI_CLK>, 2576 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2577 2578 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2579 2580 power-domains = <&dispcc MDSS_GDSC>; 2581 2582 interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>; 2583 interconnect-names = "mdp0-mem"; 2584 2585 iommus = <&apps_smmu 0x1c00 0x2>; 2586 2587 #address-cells = <2>; 2588 #size-cells = <2>; 2589 ranges; 2590 2591 status = "disabled"; 2592 2593 mdss_mdp: display-controller@ae01000 { 2594 compatible = "qcom,sm8550-dpu"; 2595 reg = <0 0x0ae01000 0 0x8f000>, 2596 <0 0x0aeb0000 0 0x2008>; 2597 reg-names = "mdp", "vbif"; 2598 2599 interrupt-parent = <&mdss>; 2600 interrupts = <0>; 2601 2602 clocks = <&gcc GCC_DISP_AHB_CLK>, 2603 <&gcc GCC_DISP_HF_AXI_CLK>, 2604 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2605 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2606 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2607 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2608 clock-names = "bus", 2609 "nrt_bus", 2610 "iface", 2611 "lut", 2612 "core", 2613 "vsync"; 2614 2615 power-domains = <&rpmhpd RPMHPD_MMCX>; 2616 2617 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2618 assigned-clock-rates = <19200000>; 2619 2620 operating-points-v2 = <&mdp_opp_table>; 2621 2622 ports { 2623 #address-cells = <1>; 2624 #size-cells = <0>; 2625 2626 port@0 { 2627 reg = <0>; 2628 dpu_intf1_out: endpoint { 2629 remote-endpoint = <&mdss_dsi0_in>; 2630 }; 2631 }; 2632 2633 port@1 { 2634 reg = <1>; 2635 dpu_intf2_out: endpoint { 2636 remote-endpoint = <&mdss_dsi1_in>; 2637 }; 2638 }; 2639 2640 port@2 { 2641 reg = <2>; 2642 dpu_intf0_out: endpoint { 2643 remote-endpoint = <&mdss_dp0_in>; 2644 }; 2645 }; 2646 }; 2647 2648 mdp_opp_table: opp-table { 2649 compatible = "operating-points-v2"; 2650 2651 opp-200000000 { 2652 opp-hz = /bits/ 64 <200000000>; 2653 required-opps = <&rpmhpd_opp_low_svs>; 2654 }; 2655 2656 opp-325000000 { 2657 opp-hz = /bits/ 64 <325000000>; 2658 required-opps = <&rpmhpd_opp_svs>; 2659 }; 2660 2661 opp-375000000 { 2662 opp-hz = /bits/ 64 <375000000>; 2663 required-opps = <&rpmhpd_opp_svs_l1>; 2664 }; 2665 2666 opp-514000000 { 2667 opp-hz = /bits/ 64 <514000000>; 2668 required-opps = <&rpmhpd_opp_nom>; 2669 }; 2670 }; 2671 }; 2672 2673 mdss_dp0: displayport-controller@ae90000 { 2674 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp"; 2675 reg = <0 0xae90000 0 0x200>, 2676 <0 0xae90200 0 0x200>, 2677 <0 0xae90400 0 0xc00>, 2678 <0 0xae91000 0 0x400>, 2679 <0 0xae91400 0 0x400>; 2680 interrupt-parent = <&mdss>; 2681 interrupts = <12>; 2682 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2683 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2684 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2685 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2686 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2687 clock-names = "core_iface", 2688 "core_aux", 2689 "ctrl_link", 2690 "ctrl_link_iface", 2691 "stream_pixel"; 2692 2693 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2694 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2695 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2696 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2697 2698 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2699 phy-names = "dp"; 2700 2701 #sound-dai-cells = <0>; 2702 2703 operating-points-v2 = <&dp_opp_table>; 2704 power-domains = <&rpmhpd RPMHPD_MMCX>; 2705 2706 status = "disabled"; 2707 2708 ports { 2709 #address-cells = <1>; 2710 #size-cells = <0>; 2711 2712 port@0 { 2713 reg = <0>; 2714 mdss_dp0_in: endpoint { 2715 remote-endpoint = <&dpu_intf0_out>; 2716 }; 2717 }; 2718 2719 port@1 { 2720 reg = <1>; 2721 mdss_dp0_out: endpoint { 2722 }; 2723 }; 2724 }; 2725 2726 dp_opp_table: opp-table { 2727 compatible = "operating-points-v2"; 2728 2729 opp-162000000 { 2730 opp-hz = /bits/ 64 <162000000>; 2731 required-opps = <&rpmhpd_opp_low_svs_d1>; 2732 }; 2733 2734 opp-270000000 { 2735 opp-hz = /bits/ 64 <270000000>; 2736 required-opps = <&rpmhpd_opp_low_svs>; 2737 }; 2738 2739 opp-540000000 { 2740 opp-hz = /bits/ 64 <540000000>; 2741 required-opps = <&rpmhpd_opp_svs_l1>; 2742 }; 2743 2744 opp-810000000 { 2745 opp-hz = /bits/ 64 <810000000>; 2746 required-opps = <&rpmhpd_opp_nom>; 2747 }; 2748 }; 2749 }; 2750 2751 mdss_dsi0: dsi@ae94000 { 2752 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2753 reg = <0 0x0ae94000 0 0x400>; 2754 reg-names = "dsi_ctrl"; 2755 2756 interrupt-parent = <&mdss>; 2757 interrupts = <4>; 2758 2759 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2760 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2761 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2762 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2763 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2764 <&gcc GCC_DISP_HF_AXI_CLK>; 2765 clock-names = "byte", 2766 "byte_intf", 2767 "pixel", 2768 "core", 2769 "iface", 2770 "bus"; 2771 2772 power-domains = <&rpmhpd RPMHPD_MMCX>; 2773 2774 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2775 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2776 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2777 <&mdss_dsi0_phy 1>; 2778 2779 operating-points-v2 = <&mdss_dsi_opp_table>; 2780 2781 phys = <&mdss_dsi0_phy>; 2782 phy-names = "dsi"; 2783 2784 #address-cells = <1>; 2785 #size-cells = <0>; 2786 2787 status = "disabled"; 2788 2789 ports { 2790 #address-cells = <1>; 2791 #size-cells = <0>; 2792 2793 port@0 { 2794 reg = <0>; 2795 mdss_dsi0_in: endpoint { 2796 remote-endpoint = <&dpu_intf1_out>; 2797 }; 2798 }; 2799 2800 port@1 { 2801 reg = <1>; 2802 mdss_dsi0_out: endpoint { 2803 }; 2804 }; 2805 }; 2806 2807 mdss_dsi_opp_table: opp-table { 2808 compatible = "operating-points-v2"; 2809 2810 opp-187500000 { 2811 opp-hz = /bits/ 64 <187500000>; 2812 required-opps = <&rpmhpd_opp_low_svs>; 2813 }; 2814 2815 opp-300000000 { 2816 opp-hz = /bits/ 64 <300000000>; 2817 required-opps = <&rpmhpd_opp_svs>; 2818 }; 2819 2820 opp-358000000 { 2821 opp-hz = /bits/ 64 <358000000>; 2822 required-opps = <&rpmhpd_opp_svs_l1>; 2823 }; 2824 }; 2825 }; 2826 2827 mdss_dsi0_phy: phy@ae95000 { 2828 compatible = "qcom,sm8550-dsi-phy-4nm"; 2829 reg = <0 0x0ae95000 0 0x200>, 2830 <0 0x0ae95200 0 0x280>, 2831 <0 0x0ae95500 0 0x400>; 2832 reg-names = "dsi_phy", 2833 "dsi_phy_lane", 2834 "dsi_pll"; 2835 2836 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2837 <&rpmhcc RPMH_CXO_CLK>; 2838 clock-names = "iface", "ref"; 2839 2840 #clock-cells = <1>; 2841 #phy-cells = <0>; 2842 2843 status = "disabled"; 2844 }; 2845 2846 mdss_dsi1: dsi@ae96000 { 2847 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2848 reg = <0 0x0ae96000 0 0x400>; 2849 reg-names = "dsi_ctrl"; 2850 2851 interrupt-parent = <&mdss>; 2852 interrupts = <5>; 2853 2854 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2855 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2856 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2857 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2858 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2859 <&gcc GCC_DISP_HF_AXI_CLK>; 2860 clock-names = "byte", 2861 "byte_intf", 2862 "pixel", 2863 "core", 2864 "iface", 2865 "bus"; 2866 2867 power-domains = <&rpmhpd RPMHPD_MMCX>; 2868 2869 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2870 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2871 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2872 <&mdss_dsi1_phy 1>; 2873 2874 operating-points-v2 = <&mdss_dsi_opp_table>; 2875 2876 phys = <&mdss_dsi1_phy>; 2877 phy-names = "dsi"; 2878 2879 #address-cells = <1>; 2880 #size-cells = <0>; 2881 2882 status = "disabled"; 2883 2884 ports { 2885 #address-cells = <1>; 2886 #size-cells = <0>; 2887 2888 port@0 { 2889 reg = <0>; 2890 mdss_dsi1_in: endpoint { 2891 remote-endpoint = <&dpu_intf2_out>; 2892 }; 2893 }; 2894 2895 port@1 { 2896 reg = <1>; 2897 mdss_dsi1_out: endpoint { 2898 }; 2899 }; 2900 }; 2901 }; 2902 2903 mdss_dsi1_phy: phy@ae97000 { 2904 compatible = "qcom,sm8550-dsi-phy-4nm"; 2905 reg = <0 0x0ae97000 0 0x200>, 2906 <0 0x0ae97200 0 0x280>, 2907 <0 0x0ae97500 0 0x400>; 2908 reg-names = "dsi_phy", 2909 "dsi_phy_lane", 2910 "dsi_pll"; 2911 2912 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2913 <&rpmhcc RPMH_CXO_CLK>; 2914 clock-names = "iface", "ref"; 2915 2916 #clock-cells = <1>; 2917 #phy-cells = <0>; 2918 2919 status = "disabled"; 2920 }; 2921 }; 2922 2923 dispcc: clock-controller@af00000 { 2924 compatible = "qcom,sm8550-dispcc"; 2925 reg = <0 0x0af00000 0 0x20000>; 2926 clocks = <&bi_tcxo_div2>, 2927 <&bi_tcxo_ao_div2>, 2928 <&gcc GCC_DISP_AHB_CLK>, 2929 <&sleep_clk>, 2930 <&mdss_dsi0_phy 0>, 2931 <&mdss_dsi0_phy 1>, 2932 <&mdss_dsi1_phy 0>, 2933 <&mdss_dsi1_phy 1>, 2934 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2935 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2936 <0>, /* dp1 */ 2937 <0>, 2938 <0>, /* dp2 */ 2939 <0>, 2940 <0>, /* dp3 */ 2941 <0>; 2942 power-domains = <&rpmhpd RPMHPD_MMCX>; 2943 required-opps = <&rpmhpd_opp_low_svs>; 2944 #clock-cells = <1>; 2945 #reset-cells = <1>; 2946 #power-domain-cells = <1>; 2947 }; 2948 2949 usb_1_hsphy: phy@88e3000 { 2950 compatible = "qcom,sm8550-snps-eusb2-phy"; 2951 reg = <0x0 0x088e3000 0x0 0x154>; 2952 #phy-cells = <0>; 2953 2954 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 2955 clock-names = "ref"; 2956 2957 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2958 2959 status = "disabled"; 2960 }; 2961 2962 usb_dp_qmpphy: phy@88e8000 { 2963 compatible = "qcom,sm8550-qmp-usb3-dp-phy"; 2964 reg = <0x0 0x088e8000 0x0 0x3000>; 2965 2966 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2967 <&rpmhcc RPMH_CXO_CLK>, 2968 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2969 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2970 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2971 2972 power-domains = <&gcc USB3_PHY_GDSC>; 2973 2974 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2975 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2976 reset-names = "phy", "common"; 2977 2978 #clock-cells = <1>; 2979 #phy-cells = <1>; 2980 2981 status = "disabled"; 2982 2983 ports { 2984 #address-cells = <1>; 2985 #size-cells = <0>; 2986 2987 port@0 { 2988 reg = <0>; 2989 2990 usb_dp_qmpphy_out: endpoint { 2991 }; 2992 }; 2993 2994 port@1 { 2995 reg = <1>; 2996 2997 usb_dp_qmpphy_usb_ss_in: endpoint { 2998 }; 2999 }; 3000 3001 port@2 { 3002 reg = <2>; 3003 3004 usb_dp_qmpphy_dp_in: endpoint { 3005 }; 3006 }; 3007 }; 3008 }; 3009 3010 usb_1: usb@a6f8800 { 3011 compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; 3012 reg = <0x0 0x0a6f8800 0x0 0x400>; 3013 #address-cells = <2>; 3014 #size-cells = <2>; 3015 ranges; 3016 3017 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3018 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3019 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3020 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3021 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3022 <&tcsr TCSR_USB3_CLKREF_EN>; 3023 clock-names = "cfg_noc", 3024 "core", 3025 "iface", 3026 "sleep", 3027 "mock_utmi", 3028 "xo"; 3029 3030 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3031 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3032 assigned-clock-rates = <19200000>, <200000000>; 3033 3034 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3035 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3036 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3037 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3038 interrupt-names = "hs_phy_irq", 3039 "ss_phy_irq", 3040 "dm_hs_phy_irq", 3041 "dp_hs_phy_irq"; 3042 3043 power-domains = <&gcc USB30_PRIM_GDSC>; 3044 required-opps = <&rpmhpd_opp_nom>; 3045 3046 resets = <&gcc GCC_USB30_PRIM_BCR>; 3047 3048 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3049 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3050 interconnect-names = "usb-ddr", "apps-usb"; 3051 3052 status = "disabled"; 3053 3054 usb_1_dwc3: usb@a600000 { 3055 compatible = "snps,dwc3"; 3056 reg = <0x0 0x0a600000 0x0 0xcd00>; 3057 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3058 iommus = <&apps_smmu 0x40 0x0>; 3059 snps,dis_u2_susphy_quirk; 3060 snps,dis_enblslpm_quirk; 3061 snps,usb3_lpm_capable; 3062 phys = <&usb_1_hsphy>, 3063 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 3064 phy-names = "usb2-phy", "usb3-phy"; 3065 3066 ports { 3067 #address-cells = <1>; 3068 #size-cells = <0>; 3069 3070 port@0 { 3071 reg = <0>; 3072 3073 usb_1_dwc3_hs: endpoint { 3074 }; 3075 }; 3076 3077 port@1 { 3078 reg = <1>; 3079 3080 usb_1_dwc3_ss: endpoint { 3081 }; 3082 }; 3083 }; 3084 }; 3085 }; 3086 3087 pdc: interrupt-controller@b220000 { 3088 compatible = "qcom,sm8550-pdc", "qcom,pdc"; 3089 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3090 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3091 <125 63 1>, <126 716 12>, 3092 <138 251 5>; 3093 #interrupt-cells = <2>; 3094 interrupt-parent = <&intc>; 3095 interrupt-controller; 3096 }; 3097 3098 tsens0: thermal-sensor@c271000 { 3099 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3100 reg = <0 0x0c271000 0 0x1000>, /* TM */ 3101 <0 0x0c222000 0 0x1000>; /* SROT */ 3102 #qcom,sensors = <16>; 3103 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3105 interrupt-names = "uplow", "critical"; 3106 #thermal-sensor-cells = <1>; 3107 }; 3108 3109 tsens1: thermal-sensor@c272000 { 3110 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3111 reg = <0 0x0c272000 0 0x1000>, /* TM */ 3112 <0 0x0c223000 0 0x1000>; /* SROT */ 3113 #qcom,sensors = <16>; 3114 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 3116 interrupt-names = "uplow", "critical"; 3117 #thermal-sensor-cells = <1>; 3118 }; 3119 3120 tsens2: thermal-sensor@c273000 { 3121 compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; 3122 reg = <0 0x0c273000 0 0x1000>, /* TM */ 3123 <0 0x0c224000 0 0x1000>; /* SROT */ 3124 #qcom,sensors = <16>; 3125 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 3127 interrupt-names = "uplow", "critical"; 3128 #thermal-sensor-cells = <1>; 3129 }; 3130 3131 aoss_qmp: power-management@c300000 { 3132 compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; 3133 reg = <0 0x0c300000 0 0x400>; 3134 interrupt-parent = <&ipcc>; 3135 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3136 IRQ_TYPE_EDGE_RISING>; 3137 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3138 3139 #clock-cells = <0>; 3140 }; 3141 3142 sram@c3f0000 { 3143 compatible = "qcom,rpmh-stats"; 3144 reg = <0 0x0c3f0000 0 0x400>; 3145 }; 3146 3147 spmi_bus: spmi@c400000 { 3148 compatible = "qcom,spmi-pmic-arb"; 3149 reg = <0 0x0c400000 0 0x3000>, 3150 <0 0x0c500000 0 0x400000>, 3151 <0 0x0c440000 0 0x80000>, 3152 <0 0x0c4c0000 0 0x20000>, 3153 <0 0x0c42d000 0 0x4000>; 3154 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3155 interrupt-names = "periph_irq"; 3156 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3157 qcom,ee = <0>; 3158 qcom,channel = <0>; 3159 qcom,bus-id = <0>; 3160 #address-cells = <2>; 3161 #size-cells = <0>; 3162 interrupt-controller; 3163 #interrupt-cells = <4>; 3164 }; 3165 3166 tlmm: pinctrl@f100000 { 3167 compatible = "qcom,sm8550-tlmm"; 3168 reg = <0 0x0f100000 0 0x300000>; 3169 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3170 gpio-controller; 3171 #gpio-cells = <2>; 3172 interrupt-controller; 3173 #interrupt-cells = <2>; 3174 gpio-ranges = <&tlmm 0 0 211>; 3175 wakeup-parent = <&pdc>; 3176 3177 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3178 /* SDA, SCL */ 3179 pins = "gpio16", "gpio17"; 3180 function = "i2chub0_se0"; 3181 drive-strength = <2>; 3182 bias-pull-up; 3183 }; 3184 3185 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3186 /* SDA, SCL */ 3187 pins = "gpio18", "gpio19"; 3188 function = "i2chub0_se1"; 3189 drive-strength = <2>; 3190 bias-pull-up; 3191 }; 3192 3193 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3194 /* SDA, SCL */ 3195 pins = "gpio20", "gpio21"; 3196 function = "i2chub0_se2"; 3197 drive-strength = <2>; 3198 bias-pull-up; 3199 }; 3200 3201 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3202 /* SDA, SCL */ 3203 pins = "gpio22", "gpio23"; 3204 function = "i2chub0_se3"; 3205 drive-strength = <2>; 3206 bias-pull-up; 3207 }; 3208 3209 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3210 /* SDA, SCL */ 3211 pins = "gpio4", "gpio5"; 3212 function = "i2chub0_se4"; 3213 drive-strength = <2>; 3214 bias-pull-up; 3215 }; 3216 3217 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 3218 /* SDA, SCL */ 3219 pins = "gpio6", "gpio7"; 3220 function = "i2chub0_se5"; 3221 drive-strength = <2>; 3222 bias-pull-up; 3223 }; 3224 3225 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 3226 /* SDA, SCL */ 3227 pins = "gpio8", "gpio9"; 3228 function = "i2chub0_se6"; 3229 drive-strength = <2>; 3230 bias-pull-up; 3231 }; 3232 3233 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 3234 /* SDA, SCL */ 3235 pins = "gpio10", "gpio11"; 3236 function = "i2chub0_se7"; 3237 drive-strength = <2>; 3238 bias-pull-up; 3239 }; 3240 3241 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 3242 /* SDA, SCL */ 3243 pins = "gpio206", "gpio207"; 3244 function = "i2chub0_se8"; 3245 drive-strength = <2>; 3246 bias-pull-up; 3247 }; 3248 3249 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 3250 /* SDA, SCL */ 3251 pins = "gpio84", "gpio85"; 3252 function = "i2chub0_se9"; 3253 drive-strength = <2>; 3254 bias-pull-up; 3255 }; 3256 3257 pcie0_default_state: pcie0-default-state { 3258 perst-pins { 3259 pins = "gpio94"; 3260 function = "gpio"; 3261 drive-strength = <2>; 3262 bias-pull-down; 3263 }; 3264 3265 clkreq-pins { 3266 pins = "gpio95"; 3267 function = "pcie0_clk_req_n"; 3268 drive-strength = <2>; 3269 bias-pull-up; 3270 }; 3271 3272 wake-pins { 3273 pins = "gpio96"; 3274 function = "gpio"; 3275 drive-strength = <2>; 3276 bias-pull-up; 3277 }; 3278 }; 3279 3280 pcie1_default_state: pcie1-default-state { 3281 perst-pins { 3282 pins = "gpio97"; 3283 function = "gpio"; 3284 drive-strength = <2>; 3285 bias-pull-down; 3286 }; 3287 3288 clkreq-pins { 3289 pins = "gpio98"; 3290 function = "pcie1_clk_req_n"; 3291 drive-strength = <2>; 3292 bias-pull-up; 3293 }; 3294 3295 wake-pins { 3296 pins = "gpio99"; 3297 function = "gpio"; 3298 drive-strength = <2>; 3299 bias-pull-up; 3300 }; 3301 }; 3302 3303 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3304 /* SDA, SCL */ 3305 pins = "gpio28", "gpio29"; 3306 function = "qup1_se0"; 3307 drive-strength = <2>; 3308 bias-pull-up = <2200>; 3309 }; 3310 3311 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3312 /* SDA, SCL */ 3313 pins = "gpio32", "gpio33"; 3314 function = "qup1_se1"; 3315 drive-strength = <2>; 3316 bias-pull-up = <2200>; 3317 }; 3318 3319 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3320 /* SDA, SCL */ 3321 pins = "gpio36", "gpio37"; 3322 function = "qup1_se2"; 3323 drive-strength = <2>; 3324 bias-pull-up = <2200>; 3325 }; 3326 3327 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3328 /* SDA, SCL */ 3329 pins = "gpio40", "gpio41"; 3330 function = "qup1_se3"; 3331 drive-strength = <2>; 3332 bias-pull-up = <2200>; 3333 }; 3334 3335 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3336 /* SDA, SCL */ 3337 pins = "gpio44", "gpio45"; 3338 function = "qup1_se4"; 3339 drive-strength = <2>; 3340 bias-pull-up = <2200>; 3341 }; 3342 3343 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3344 /* SDA, SCL */ 3345 pins = "gpio52", "gpio53"; 3346 function = "qup1_se5"; 3347 drive-strength = <2>; 3348 bias-pull-up = <2200>; 3349 }; 3350 3351 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3352 /* SDA, SCL */ 3353 pins = "gpio48", "gpio49"; 3354 function = "qup1_se6"; 3355 drive-strength = <2>; 3356 bias-pull-up = <2200>; 3357 }; 3358 3359 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3360 scl-pins { 3361 pins = "gpio57"; 3362 function = "qup2_se0_l1_mira"; 3363 drive-strength = <2>; 3364 bias-pull-up = <2200>; 3365 }; 3366 3367 sda-pins { 3368 pins = "gpio56"; 3369 function = "qup2_se0_l0_mira"; 3370 drive-strength = <2>; 3371 bias-pull-up = <2200>; 3372 }; 3373 }; 3374 3375 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3376 /* SDA, SCL */ 3377 pins = "gpio60", "gpio61"; 3378 function = "qup2_se1"; 3379 drive-strength = <2>; 3380 bias-pull-up = <2200>; 3381 }; 3382 3383 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3384 /* SDA, SCL */ 3385 pins = "gpio64", "gpio65"; 3386 function = "qup2_se2"; 3387 drive-strength = <2>; 3388 bias-pull-up = <2200>; 3389 }; 3390 3391 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3392 /* SDA, SCL */ 3393 pins = "gpio68", "gpio69"; 3394 function = "qup2_se3"; 3395 drive-strength = <2>; 3396 bias-pull-up = <2200>; 3397 }; 3398 3399 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3400 /* SDA, SCL */ 3401 pins = "gpio2", "gpio3"; 3402 function = "qup2_se4"; 3403 drive-strength = <2>; 3404 bias-pull-up = <2200>; 3405 }; 3406 3407 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3408 /* SDA, SCL */ 3409 pins = "gpio80", "gpio81"; 3410 function = "qup2_se5"; 3411 drive-strength = <2>; 3412 bias-pull-up = <2200>; 3413 }; 3414 3415 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3416 /* SDA, SCL */ 3417 pins = "gpio72", "gpio106"; 3418 function = "qup2_se7"; 3419 drive-strength = <2>; 3420 bias-pull-up = <2200>; 3421 }; 3422 3423 qup_spi0_cs: qup-spi0-cs-state { 3424 pins = "gpio31"; 3425 function = "qup1_se0"; 3426 drive-strength = <6>; 3427 bias-disable; 3428 }; 3429 3430 qup_spi0_data_clk: qup-spi0-data-clk-state { 3431 /* MISO, MOSI, CLK */ 3432 pins = "gpio28", "gpio29", "gpio30"; 3433 function = "qup1_se0"; 3434 drive-strength = <6>; 3435 bias-disable; 3436 }; 3437 3438 qup_spi1_cs: qup-spi1-cs-state { 3439 pins = "gpio35"; 3440 function = "qup1_se1"; 3441 drive-strength = <6>; 3442 bias-disable; 3443 }; 3444 3445 qup_spi1_data_clk: qup-spi1-data-clk-state { 3446 /* MISO, MOSI, CLK */ 3447 pins = "gpio32", "gpio33", "gpio34"; 3448 function = "qup1_se1"; 3449 drive-strength = <6>; 3450 bias-disable; 3451 }; 3452 3453 qup_spi2_cs: qup-spi2-cs-state { 3454 pins = "gpio39"; 3455 function = "qup1_se2"; 3456 drive-strength = <6>; 3457 bias-disable; 3458 }; 3459 3460 qup_spi2_data_clk: qup-spi2-data-clk-state { 3461 /* MISO, MOSI, CLK */ 3462 pins = "gpio36", "gpio37", "gpio38"; 3463 function = "qup1_se2"; 3464 drive-strength = <6>; 3465 bias-disable; 3466 }; 3467 3468 qup_spi3_cs: qup-spi3-cs-state { 3469 pins = "gpio43"; 3470 function = "qup1_se3"; 3471 drive-strength = <6>; 3472 bias-disable; 3473 }; 3474 3475 qup_spi3_data_clk: qup-spi3-data-clk-state { 3476 /* MISO, MOSI, CLK */ 3477 pins = "gpio40", "gpio41", "gpio42"; 3478 function = "qup1_se3"; 3479 drive-strength = <6>; 3480 bias-disable; 3481 }; 3482 3483 qup_spi4_cs: qup-spi4-cs-state { 3484 pins = "gpio47"; 3485 function = "qup1_se4"; 3486 drive-strength = <6>; 3487 bias-disable; 3488 }; 3489 3490 qup_spi4_data_clk: qup-spi4-data-clk-state { 3491 /* MISO, MOSI, CLK */ 3492 pins = "gpio44", "gpio45", "gpio46"; 3493 function = "qup1_se4"; 3494 drive-strength = <6>; 3495 bias-disable; 3496 }; 3497 3498 qup_spi5_cs: qup-spi5-cs-state { 3499 pins = "gpio55"; 3500 function = "qup1_se5"; 3501 drive-strength = <6>; 3502 bias-disable; 3503 }; 3504 3505 qup_spi5_data_clk: qup-spi5-data-clk-state { 3506 /* MISO, MOSI, CLK */ 3507 pins = "gpio52", "gpio53", "gpio54"; 3508 function = "qup1_se5"; 3509 drive-strength = <6>; 3510 bias-disable; 3511 }; 3512 3513 qup_spi6_cs: qup-spi6-cs-state { 3514 pins = "gpio51"; 3515 function = "qup1_se6"; 3516 drive-strength = <6>; 3517 bias-disable; 3518 }; 3519 3520 qup_spi6_data_clk: qup-spi6-data-clk-state { 3521 /* MISO, MOSI, CLK */ 3522 pins = "gpio48", "gpio49", "gpio50"; 3523 function = "qup1_se6"; 3524 drive-strength = <6>; 3525 bias-disable; 3526 }; 3527 3528 qup_spi8_cs: qup-spi8-cs-state { 3529 pins = "gpio59"; 3530 function = "qup2_se0_l3_mira"; 3531 drive-strength = <6>; 3532 bias-disable; 3533 }; 3534 3535 qup_spi8_data_clk: qup-spi8-data-clk-state { 3536 /* MISO, MOSI, CLK */ 3537 pins = "gpio56", "gpio57", "gpio58"; 3538 function = "qup2_se0_l2_mira"; 3539 drive-strength = <6>; 3540 bias-disable; 3541 }; 3542 3543 qup_spi9_cs: qup-spi9-cs-state { 3544 pins = "gpio63"; 3545 function = "qup2_se1"; 3546 drive-strength = <6>; 3547 bias-disable; 3548 }; 3549 3550 qup_spi9_data_clk: qup-spi9-data-clk-state { 3551 /* MISO, MOSI, CLK */ 3552 pins = "gpio60", "gpio61", "gpio62"; 3553 function = "qup2_se1"; 3554 drive-strength = <6>; 3555 bias-disable; 3556 }; 3557 3558 qup_spi10_cs: qup-spi10-cs-state { 3559 pins = "gpio67"; 3560 function = "qup2_se2"; 3561 drive-strength = <6>; 3562 bias-disable; 3563 }; 3564 3565 qup_spi10_data_clk: qup-spi10-data-clk-state { 3566 /* MISO, MOSI, CLK */ 3567 pins = "gpio64", "gpio65", "gpio66"; 3568 function = "qup2_se2"; 3569 drive-strength = <6>; 3570 bias-disable; 3571 }; 3572 3573 qup_spi11_cs: qup-spi11-cs-state { 3574 pins = "gpio71"; 3575 function = "qup2_se3"; 3576 drive-strength = <6>; 3577 bias-disable; 3578 }; 3579 3580 qup_spi11_data_clk: qup-spi11-data-clk-state { 3581 /* MISO, MOSI, CLK */ 3582 pins = "gpio68", "gpio69", "gpio70"; 3583 function = "qup2_se3"; 3584 drive-strength = <6>; 3585 bias-disable; 3586 }; 3587 3588 qup_spi12_cs: qup-spi12-cs-state { 3589 pins = "gpio119"; 3590 function = "qup2_se4"; 3591 drive-strength = <6>; 3592 bias-disable; 3593 }; 3594 3595 qup_spi12_data_clk: qup-spi12-data-clk-state { 3596 /* MISO, MOSI, CLK */ 3597 pins = "gpio2", "gpio3", "gpio118"; 3598 function = "qup2_se4"; 3599 drive-strength = <6>; 3600 bias-disable; 3601 }; 3602 3603 qup_spi13_cs: qup-spi13-cs-state { 3604 pins = "gpio83"; 3605 function = "qup2_se5"; 3606 drive-strength = <6>; 3607 bias-disable; 3608 }; 3609 3610 qup_spi13_data_clk: qup-spi13-data-clk-state { 3611 /* MISO, MOSI, CLK */ 3612 pins = "gpio80", "gpio81", "gpio82"; 3613 function = "qup2_se5"; 3614 drive-strength = <6>; 3615 bias-disable; 3616 }; 3617 3618 qup_spi15_cs: qup-spi15-cs-state { 3619 pins = "gpio75"; 3620 function = "qup2_se7"; 3621 drive-strength = <6>; 3622 bias-disable; 3623 }; 3624 3625 qup_spi15_data_clk: qup-spi15-data-clk-state { 3626 /* MISO, MOSI, CLK */ 3627 pins = "gpio72", "gpio106", "gpio74"; 3628 function = "qup2_se7"; 3629 drive-strength = <6>; 3630 bias-disable; 3631 }; 3632 3633 qup_uart7_default: qup-uart7-default-state { 3634 /* TX, RX */ 3635 pins = "gpio26", "gpio27"; 3636 function = "qup1_se7"; 3637 drive-strength = <2>; 3638 bias-disable; 3639 }; 3640 3641 sdc2_sleep: sdc2-sleep-state { 3642 clk-pins { 3643 pins = "sdc2_clk"; 3644 bias-disable; 3645 drive-strength = <2>; 3646 }; 3647 3648 cmd-pins { 3649 pins = "sdc2_cmd"; 3650 bias-pull-up; 3651 drive-strength = <2>; 3652 }; 3653 3654 data-pins { 3655 pins = "sdc2_data"; 3656 bias-pull-up; 3657 drive-strength = <2>; 3658 }; 3659 }; 3660 3661 sdc2_default: sdc2-default-state { 3662 clk-pins { 3663 pins = "sdc2_clk"; 3664 bias-disable; 3665 drive-strength = <16>; 3666 }; 3667 3668 cmd-pins { 3669 pins = "sdc2_cmd"; 3670 bias-pull-up; 3671 drive-strength = <10>; 3672 }; 3673 3674 data-pins { 3675 pins = "sdc2_data"; 3676 bias-pull-up; 3677 drive-strength = <10>; 3678 }; 3679 }; 3680 }; 3681 3682 apps_smmu: iommu@15000000 { 3683 compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3684 reg = <0 0x15000000 0 0x100000>; 3685 #iommu-cells = <2>; 3686 #global-interrupts = <1>; 3687 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3692 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3695 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3696 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3697 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 3784 }; 3785 3786 intc: interrupt-controller@17100000 { 3787 compatible = "arm,gic-v3"; 3788 reg = <0 0x17100000 0 0x10000>, /* GICD */ 3789 <0 0x17180000 0 0x200000>; /* GICR * 8 */ 3790 ranges; 3791 #interrupt-cells = <3>; 3792 interrupt-controller; 3793 #redistributor-regions = <1>; 3794 redistributor-stride = <0 0x40000>; 3795 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 3796 #address-cells = <2>; 3797 #size-cells = <2>; 3798 3799 gic_its: msi-controller@17140000 { 3800 compatible = "arm,gic-v3-its"; 3801 reg = <0 0x17140000 0 0x20000>; 3802 msi-controller; 3803 #msi-cells = <1>; 3804 }; 3805 }; 3806 3807 timer@17420000 { 3808 compatible = "arm,armv7-timer-mem"; 3809 reg = <0 0x17420000 0 0x1000>; 3810 ranges = <0 0 0 0x20000000>; 3811 #address-cells = <1>; 3812 #size-cells = <1>; 3813 3814 frame@17421000 { 3815 reg = <0x17421000 0x1000>, 3816 <0x17422000 0x1000>; 3817 frame-number = <0>; 3818 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3820 }; 3821 3822 frame@17423000 { 3823 reg = <0x17423000 0x1000>; 3824 frame-number = <1>; 3825 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3826 status = "disabled"; 3827 }; 3828 3829 frame@17425000 { 3830 reg = <0x17425000 0x1000>; 3831 frame-number = <2>; 3832 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3833 status = "disabled"; 3834 }; 3835 3836 frame@17427000 { 3837 reg = <0x17427000 0x1000>; 3838 frame-number = <3>; 3839 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3840 status = "disabled"; 3841 }; 3842 3843 frame@17429000 { 3844 reg = <0x17429000 0x1000>; 3845 frame-number = <4>; 3846 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3847 status = "disabled"; 3848 }; 3849 3850 frame@1742b000 { 3851 reg = <0x1742b000 0x1000>; 3852 frame-number = <5>; 3853 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3854 status = "disabled"; 3855 }; 3856 3857 frame@1742d000 { 3858 reg = <0x1742d000 0x1000>; 3859 frame-number = <6>; 3860 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3861 status = "disabled"; 3862 }; 3863 }; 3864 3865 apps_rsc: rsc@17a00000 { 3866 label = "apps_rsc"; 3867 compatible = "qcom,rpmh-rsc"; 3868 reg = <0 0x17a00000 0 0x10000>, 3869 <0 0x17a10000 0 0x10000>, 3870 <0 0x17a20000 0 0x10000>, 3871 <0 0x17a30000 0 0x10000>; 3872 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 3873 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3876 qcom,tcs-offset = <0xd00>; 3877 qcom,drv-id = <2>; 3878 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3879 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3880 power-domains = <&CLUSTER_PD>; 3881 3882 apps_bcm_voter: bcm-voter { 3883 compatible = "qcom,bcm-voter"; 3884 }; 3885 3886 rpmhcc: clock-controller { 3887 compatible = "qcom,sm8550-rpmh-clk"; 3888 #clock-cells = <1>; 3889 clock-names = "xo"; 3890 clocks = <&xo_board>; 3891 }; 3892 3893 rpmhpd: power-controller { 3894 compatible = "qcom,sm8550-rpmhpd"; 3895 #power-domain-cells = <1>; 3896 operating-points-v2 = <&rpmhpd_opp_table>; 3897 3898 rpmhpd_opp_table: opp-table { 3899 compatible = "operating-points-v2"; 3900 3901 rpmhpd_opp_ret: opp-16 { 3902 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3903 }; 3904 3905 rpmhpd_opp_min_svs: opp-48 { 3906 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3907 }; 3908 3909 rpmhpd_opp_low_svs_d2: opp-52 { 3910 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3911 }; 3912 3913 rpmhpd_opp_low_svs_d1: opp-56 { 3914 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3915 }; 3916 3917 rpmhpd_opp_low_svs_d0: opp-60 { 3918 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3919 }; 3920 3921 rpmhpd_opp_low_svs: opp-64 { 3922 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3923 }; 3924 3925 rpmhpd_opp_low_svs_l1: opp-80 { 3926 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3927 }; 3928 3929 rpmhpd_opp_svs: opp-128 { 3930 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3931 }; 3932 3933 rpmhpd_opp_svs_l0: opp-144 { 3934 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3935 }; 3936 3937 rpmhpd_opp_svs_l1: opp-192 { 3938 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3939 }; 3940 3941 rpmhpd_opp_nom: opp-256 { 3942 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3943 }; 3944 3945 rpmhpd_opp_nom_l1: opp-320 { 3946 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3947 }; 3948 3949 rpmhpd_opp_nom_l2: opp-336 { 3950 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3951 }; 3952 3953 rpmhpd_opp_turbo: opp-384 { 3954 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3955 }; 3956 3957 rpmhpd_opp_turbo_l1: opp-416 { 3958 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3959 }; 3960 }; 3961 }; 3962 }; 3963 3964 cpufreq_hw: cpufreq@17d91000 { 3965 compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; 3966 reg = <0 0x17d91000 0 0x1000>, 3967 <0 0x17d92000 0 0x1000>, 3968 <0 0x17d93000 0 0x1000>; 3969 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3970 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 3971 clock-names = "xo", "alternate"; 3972 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3975 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 3976 #freq-domain-cells = <1>; 3977 #clock-cells = <1>; 3978 }; 3979 3980 pmu@24091000 { 3981 compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3982 reg = <0 0x24091000 0 0x1000>; 3983 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3984 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3985 3986 operating-points-v2 = <&llcc_bwmon_opp_table>; 3987 3988 llcc_bwmon_opp_table: opp-table { 3989 compatible = "operating-points-v2"; 3990 3991 opp-0 { 3992 opp-peak-kBps = <2086000>; 3993 }; 3994 3995 opp-1 { 3996 opp-peak-kBps = <2929000>; 3997 }; 3998 3999 opp-2 { 4000 opp-peak-kBps = <5931000>; 4001 }; 4002 4003 opp-3 { 4004 opp-peak-kBps = <6515000>; 4005 }; 4006 4007 opp-4 { 4008 opp-peak-kBps = <7980000>; 4009 }; 4010 4011 opp-5 { 4012 opp-peak-kBps = <10437000>; 4013 }; 4014 4015 opp-6 { 4016 opp-peak-kBps = <12157000>; 4017 }; 4018 4019 opp-7 { 4020 opp-peak-kBps = <14060000>; 4021 }; 4022 4023 opp-8 { 4024 opp-peak-kBps = <16113000>; 4025 }; 4026 }; 4027 }; 4028 4029 pmu@240b6400 { 4030 compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; 4031 reg = <0 0x240b6400 0 0x600>; 4032 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4033 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4034 4035 operating-points-v2 = <&cpu_bwmon_opp_table>; 4036 4037 cpu_bwmon_opp_table: opp-table { 4038 compatible = "operating-points-v2"; 4039 4040 opp-0 { 4041 opp-peak-kBps = <4577000>; 4042 }; 4043 4044 opp-1 { 4045 opp-peak-kBps = <7110000>; 4046 }; 4047 4048 opp-2 { 4049 opp-peak-kBps = <9155000>; 4050 }; 4051 4052 opp-3 { 4053 opp-peak-kBps = <12298000>; 4054 }; 4055 4056 opp-4 { 4057 opp-peak-kBps = <14236000>; 4058 }; 4059 4060 opp-5 { 4061 opp-peak-kBps = <16265000>; 4062 }; 4063 }; 4064 }; 4065 4066 gem_noc: interconnect@24100000 { 4067 compatible = "qcom,sm8550-gem-noc"; 4068 reg = <0 0x24100000 0 0xbb800>; 4069 #interconnect-cells = <2>; 4070 qcom,bcm-voters = <&apps_bcm_voter>; 4071 }; 4072 4073 system-cache-controller@25000000 { 4074 compatible = "qcom,sm8550-llcc"; 4075 reg = <0 0x25000000 0 0x200000>, 4076 <0 0x25200000 0 0x200000>, 4077 <0 0x25400000 0 0x200000>, 4078 <0 0x25600000 0 0x200000>, 4079 <0 0x25800000 0 0x200000>; 4080 reg-names = "llcc0_base", 4081 "llcc1_base", 4082 "llcc2_base", 4083 "llcc3_base", 4084 "llcc_broadcast_base"; 4085 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4086 }; 4087 4088 nsp_noc: interconnect@320c0000 { 4089 compatible = "qcom,sm8550-nsp-noc"; 4090 reg = <0 0x320c0000 0 0xe080>; 4091 #interconnect-cells = <2>; 4092 qcom,bcm-voters = <&apps_bcm_voter>; 4093 }; 4094 4095 remoteproc_cdsp: remoteproc@32300000 { 4096 compatible = "qcom,sm8550-cdsp-pas"; 4097 reg = <0x0 0x32300000 0x0 0x10000>; 4098 4099 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4100 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4101 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4102 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4103 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 4104 interrupt-names = "wdog", "fatal", "ready", 4105 "handover", "stop-ack"; 4106 4107 clocks = <&rpmhcc RPMH_CXO_CLK>; 4108 clock-names = "xo"; 4109 4110 power-domains = <&rpmhpd RPMHPD_CX>, 4111 <&rpmhpd RPMHPD_MXC>, 4112 <&rpmhpd RPMHPD_NSP>; 4113 power-domain-names = "cx", "mxc", "nsp"; 4114 4115 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4116 4117 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 4118 4119 qcom,qmp = <&aoss_qmp>; 4120 4121 qcom,smem-states = <&smp2p_cdsp_out 0>; 4122 qcom,smem-state-names = "stop"; 4123 4124 status = "disabled"; 4125 4126 glink-edge { 4127 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4128 IPCC_MPROC_SIGNAL_GLINK_QMP 4129 IRQ_TYPE_EDGE_RISING>; 4130 mboxes = <&ipcc IPCC_CLIENT_CDSP 4131 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4132 4133 label = "cdsp"; 4134 qcom,remote-pid = <5>; 4135 4136 fastrpc { 4137 compatible = "qcom,fastrpc"; 4138 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4139 label = "cdsp"; 4140 qcom,non-secure-domain; 4141 #address-cells = <1>; 4142 #size-cells = <0>; 4143 4144 compute-cb@1 { 4145 compatible = "qcom,fastrpc-compute-cb"; 4146 reg = <1>; 4147 iommus = <&apps_smmu 0x1961 0x0>, 4148 <&apps_smmu 0x0c01 0x20>, 4149 <&apps_smmu 0x19c1 0x10>; 4150 dma-coherent; 4151 }; 4152 4153 compute-cb@2 { 4154 compatible = "qcom,fastrpc-compute-cb"; 4155 reg = <2>; 4156 iommus = <&apps_smmu 0x1962 0x0>, 4157 <&apps_smmu 0x0c02 0x20>, 4158 <&apps_smmu 0x19c2 0x10>; 4159 dma-coherent; 4160 }; 4161 4162 compute-cb@3 { 4163 compatible = "qcom,fastrpc-compute-cb"; 4164 reg = <3>; 4165 iommus = <&apps_smmu 0x1963 0x0>, 4166 <&apps_smmu 0x0c03 0x20>, 4167 <&apps_smmu 0x19c3 0x10>; 4168 dma-coherent; 4169 }; 4170 4171 compute-cb@4 { 4172 compatible = "qcom,fastrpc-compute-cb"; 4173 reg = <4>; 4174 iommus = <&apps_smmu 0x1964 0x0>, 4175 <&apps_smmu 0x0c04 0x20>, 4176 <&apps_smmu 0x19c4 0x10>; 4177 dma-coherent; 4178 }; 4179 4180 compute-cb@5 { 4181 compatible = "qcom,fastrpc-compute-cb"; 4182 reg = <5>; 4183 iommus = <&apps_smmu 0x1965 0x0>, 4184 <&apps_smmu 0x0c05 0x20>, 4185 <&apps_smmu 0x19c5 0x10>; 4186 dma-coherent; 4187 }; 4188 4189 compute-cb@6 { 4190 compatible = "qcom,fastrpc-compute-cb"; 4191 reg = <6>; 4192 iommus = <&apps_smmu 0x1966 0x0>, 4193 <&apps_smmu 0x0c06 0x20>, 4194 <&apps_smmu 0x19c6 0x10>; 4195 dma-coherent; 4196 }; 4197 4198 compute-cb@7 { 4199 compatible = "qcom,fastrpc-compute-cb"; 4200 reg = <7>; 4201 iommus = <&apps_smmu 0x1967 0x0>, 4202 <&apps_smmu 0x0c07 0x20>, 4203 <&apps_smmu 0x19c7 0x10>; 4204 dma-coherent; 4205 }; 4206 4207 compute-cb@8 { 4208 compatible = "qcom,fastrpc-compute-cb"; 4209 reg = <8>; 4210 iommus = <&apps_smmu 0x1968 0x0>, 4211 <&apps_smmu 0x0c08 0x20>, 4212 <&apps_smmu 0x19c8 0x10>; 4213 dma-coherent; 4214 }; 4215 4216 /* note: secure cb9 in downstream */ 4217 }; 4218 }; 4219 }; 4220 }; 4221 4222 thermal-zones { 4223 aoss0-thermal { 4224 polling-delay-passive = <0>; 4225 polling-delay = <0>; 4226 thermal-sensors = <&tsens0 0>; 4227 4228 trips { 4229 thermal-engine-config { 4230 temperature = <125000>; 4231 hysteresis = <1000>; 4232 type = "passive"; 4233 }; 4234 4235 reset-mon-config { 4236 temperature = <115000>; 4237 hysteresis = <5000>; 4238 type = "passive"; 4239 }; 4240 }; 4241 }; 4242 4243 cpuss0-thermal { 4244 polling-delay-passive = <0>; 4245 polling-delay = <0>; 4246 thermal-sensors = <&tsens0 1>; 4247 4248 trips { 4249 thermal-engine-config { 4250 temperature = <125000>; 4251 hysteresis = <1000>; 4252 type = "passive"; 4253 }; 4254 4255 reset-mon-config { 4256 temperature = <115000>; 4257 hysteresis = <5000>; 4258 type = "passive"; 4259 }; 4260 }; 4261 }; 4262 4263 cpuss1-thermal { 4264 polling-delay-passive = <0>; 4265 polling-delay = <0>; 4266 thermal-sensors = <&tsens0 2>; 4267 4268 trips { 4269 thermal-engine-config { 4270 temperature = <125000>; 4271 hysteresis = <1000>; 4272 type = "passive"; 4273 }; 4274 4275 reset-mon-config { 4276 temperature = <115000>; 4277 hysteresis = <5000>; 4278 type = "passive"; 4279 }; 4280 }; 4281 }; 4282 4283 cpuss2-thermal { 4284 polling-delay-passive = <0>; 4285 polling-delay = <0>; 4286 thermal-sensors = <&tsens0 3>; 4287 4288 trips { 4289 thermal-engine-config { 4290 temperature = <125000>; 4291 hysteresis = <1000>; 4292 type = "passive"; 4293 }; 4294 4295 reset-mon-config { 4296 temperature = <115000>; 4297 hysteresis = <5000>; 4298 type = "passive"; 4299 }; 4300 }; 4301 }; 4302 4303 cpuss3-thermal { 4304 polling-delay-passive = <0>; 4305 polling-delay = <0>; 4306 thermal-sensors = <&tsens0 4>; 4307 4308 trips { 4309 thermal-engine-config { 4310 temperature = <125000>; 4311 hysteresis = <1000>; 4312 type = "passive"; 4313 }; 4314 4315 reset-mon-config { 4316 temperature = <115000>; 4317 hysteresis = <5000>; 4318 type = "passive"; 4319 }; 4320 }; 4321 }; 4322 4323 cpu3-top-thermal { 4324 polling-delay-passive = <0>; 4325 polling-delay = <0>; 4326 thermal-sensors = <&tsens0 5>; 4327 4328 trips { 4329 cpu3_top_alert0: trip-point0 { 4330 temperature = <90000>; 4331 hysteresis = <2000>; 4332 type = "passive"; 4333 }; 4334 4335 cpu3_top_alert1: trip-point1 { 4336 temperature = <95000>; 4337 hysteresis = <2000>; 4338 type = "passive"; 4339 }; 4340 4341 cpu3_top_crit: cpu-critical { 4342 temperature = <110000>; 4343 hysteresis = <1000>; 4344 type = "critical"; 4345 }; 4346 }; 4347 }; 4348 4349 cpu3-bottom-thermal { 4350 polling-delay-passive = <0>; 4351 polling-delay = <0>; 4352 thermal-sensors = <&tsens0 6>; 4353 4354 trips { 4355 cpu3_bottom_alert0: trip-point0 { 4356 temperature = <90000>; 4357 hysteresis = <2000>; 4358 type = "passive"; 4359 }; 4360 4361 cpu3_bottom_alert1: trip-point1 { 4362 temperature = <95000>; 4363 hysteresis = <2000>; 4364 type = "passive"; 4365 }; 4366 4367 cpu3_bottom_crit: cpu-critical { 4368 temperature = <110000>; 4369 hysteresis = <1000>; 4370 type = "critical"; 4371 }; 4372 }; 4373 }; 4374 4375 cpu4-top-thermal { 4376 polling-delay-passive = <0>; 4377 polling-delay = <0>; 4378 thermal-sensors = <&tsens0 7>; 4379 4380 trips { 4381 cpu4_top_alert0: trip-point0 { 4382 temperature = <90000>; 4383 hysteresis = <2000>; 4384 type = "passive"; 4385 }; 4386 4387 cpu4_top_alert1: trip-point1 { 4388 temperature = <95000>; 4389 hysteresis = <2000>; 4390 type = "passive"; 4391 }; 4392 4393 cpu4_top_crit: cpu-critical { 4394 temperature = <110000>; 4395 hysteresis = <1000>; 4396 type = "critical"; 4397 }; 4398 }; 4399 }; 4400 4401 cpu4-bottom-thermal { 4402 polling-delay-passive = <0>; 4403 polling-delay = <0>; 4404 thermal-sensors = <&tsens0 8>; 4405 4406 trips { 4407 cpu4_bottom_alert0: trip-point0 { 4408 temperature = <90000>; 4409 hysteresis = <2000>; 4410 type = "passive"; 4411 }; 4412 4413 cpu4_bottom_alert1: trip-point1 { 4414 temperature = <95000>; 4415 hysteresis = <2000>; 4416 type = "passive"; 4417 }; 4418 4419 cpu4_bottom_crit: cpu-critical { 4420 temperature = <110000>; 4421 hysteresis = <1000>; 4422 type = "critical"; 4423 }; 4424 }; 4425 }; 4426 4427 cpu5-top-thermal { 4428 polling-delay-passive = <0>; 4429 polling-delay = <0>; 4430 thermal-sensors = <&tsens0 9>; 4431 4432 trips { 4433 cpu5_top_alert0: trip-point0 { 4434 temperature = <90000>; 4435 hysteresis = <2000>; 4436 type = "passive"; 4437 }; 4438 4439 cpu5_top_alert1: trip-point1 { 4440 temperature = <95000>; 4441 hysteresis = <2000>; 4442 type = "passive"; 4443 }; 4444 4445 cpu5_top_crit: cpu-critical { 4446 temperature = <110000>; 4447 hysteresis = <1000>; 4448 type = "critical"; 4449 }; 4450 }; 4451 }; 4452 4453 cpu5-bottom-thermal { 4454 polling-delay-passive = <0>; 4455 polling-delay = <0>; 4456 thermal-sensors = <&tsens0 10>; 4457 4458 trips { 4459 cpu5_bottom_alert0: trip-point0 { 4460 temperature = <90000>; 4461 hysteresis = <2000>; 4462 type = "passive"; 4463 }; 4464 4465 cpu5_bottom_alert1: trip-point1 { 4466 temperature = <95000>; 4467 hysteresis = <2000>; 4468 type = "passive"; 4469 }; 4470 4471 cpu5_bottom_crit: cpu-critical { 4472 temperature = <110000>; 4473 hysteresis = <1000>; 4474 type = "critical"; 4475 }; 4476 }; 4477 }; 4478 4479 cpu6-top-thermal { 4480 polling-delay-passive = <0>; 4481 polling-delay = <0>; 4482 thermal-sensors = <&tsens0 11>; 4483 4484 trips { 4485 cpu6_top_alert0: trip-point0 { 4486 temperature = <90000>; 4487 hysteresis = <2000>; 4488 type = "passive"; 4489 }; 4490 4491 cpu6_top_alert1: trip-point1 { 4492 temperature = <95000>; 4493 hysteresis = <2000>; 4494 type = "passive"; 4495 }; 4496 4497 cpu6_top_crit: cpu-critical { 4498 temperature = <110000>; 4499 hysteresis = <1000>; 4500 type = "critical"; 4501 }; 4502 }; 4503 }; 4504 4505 cpu6-bottom-thermal { 4506 polling-delay-passive = <0>; 4507 polling-delay = <0>; 4508 thermal-sensors = <&tsens0 12>; 4509 4510 trips { 4511 cpu6_bottom_alert0: trip-point0 { 4512 temperature = <90000>; 4513 hysteresis = <2000>; 4514 type = "passive"; 4515 }; 4516 4517 cpu6_bottom_alert1: trip-point1 { 4518 temperature = <95000>; 4519 hysteresis = <2000>; 4520 type = "passive"; 4521 }; 4522 4523 cpu6_bottom_crit: cpu-critical { 4524 temperature = <110000>; 4525 hysteresis = <1000>; 4526 type = "critical"; 4527 }; 4528 }; 4529 }; 4530 4531 cpu7-top-thermal { 4532 polling-delay-passive = <0>; 4533 polling-delay = <0>; 4534 thermal-sensors = <&tsens0 13>; 4535 4536 trips { 4537 cpu7_top_alert0: trip-point0 { 4538 temperature = <90000>; 4539 hysteresis = <2000>; 4540 type = "passive"; 4541 }; 4542 4543 cpu7_top_alert1: trip-point1 { 4544 temperature = <95000>; 4545 hysteresis = <2000>; 4546 type = "passive"; 4547 }; 4548 4549 cpu7_top_crit: cpu-critical { 4550 temperature = <110000>; 4551 hysteresis = <1000>; 4552 type = "critical"; 4553 }; 4554 }; 4555 }; 4556 4557 cpu7-middle-thermal { 4558 polling-delay-passive = <0>; 4559 polling-delay = <0>; 4560 thermal-sensors = <&tsens0 14>; 4561 4562 trips { 4563 cpu7_middle_alert0: trip-point0 { 4564 temperature = <90000>; 4565 hysteresis = <2000>; 4566 type = "passive"; 4567 }; 4568 4569 cpu7_middle_alert1: trip-point1 { 4570 temperature = <95000>; 4571 hysteresis = <2000>; 4572 type = "passive"; 4573 }; 4574 4575 cpu7_middle_crit: cpu-critical { 4576 temperature = <110000>; 4577 hysteresis = <1000>; 4578 type = "critical"; 4579 }; 4580 }; 4581 }; 4582 4583 cpu7-bottom-thermal { 4584 polling-delay-passive = <0>; 4585 polling-delay = <0>; 4586 thermal-sensors = <&tsens0 15>; 4587 4588 trips { 4589 cpu7_bottom_alert0: trip-point0 { 4590 temperature = <90000>; 4591 hysteresis = <2000>; 4592 type = "passive"; 4593 }; 4594 4595 cpu7_bottom_alert1: trip-point1 { 4596 temperature = <95000>; 4597 hysteresis = <2000>; 4598 type = "passive"; 4599 }; 4600 4601 cpu7_bottom_crit: cpu-critical { 4602 temperature = <110000>; 4603 hysteresis = <1000>; 4604 type = "critical"; 4605 }; 4606 }; 4607 }; 4608 4609 aoss1-thermal { 4610 polling-delay-passive = <0>; 4611 polling-delay = <0>; 4612 thermal-sensors = <&tsens1 0>; 4613 4614 trips { 4615 thermal-engine-config { 4616 temperature = <125000>; 4617 hysteresis = <1000>; 4618 type = "passive"; 4619 }; 4620 4621 reset-mon-config { 4622 temperature = <115000>; 4623 hysteresis = <5000>; 4624 type = "passive"; 4625 }; 4626 }; 4627 }; 4628 4629 cpu0-thermal { 4630 polling-delay-passive = <0>; 4631 polling-delay = <0>; 4632 thermal-sensors = <&tsens1 1>; 4633 4634 trips { 4635 cpu0_alert0: trip-point0 { 4636 temperature = <90000>; 4637 hysteresis = <2000>; 4638 type = "passive"; 4639 }; 4640 4641 cpu0_alert1: trip-point1 { 4642 temperature = <95000>; 4643 hysteresis = <2000>; 4644 type = "passive"; 4645 }; 4646 4647 cpu0_crit: cpu-critical { 4648 temperature = <110000>; 4649 hysteresis = <1000>; 4650 type = "critical"; 4651 }; 4652 }; 4653 }; 4654 4655 cpu1-thermal { 4656 polling-delay-passive = <0>; 4657 polling-delay = <0>; 4658 thermal-sensors = <&tsens1 2>; 4659 4660 trips { 4661 cpu1_alert0: trip-point0 { 4662 temperature = <90000>; 4663 hysteresis = <2000>; 4664 type = "passive"; 4665 }; 4666 4667 cpu1_alert1: trip-point1 { 4668 temperature = <95000>; 4669 hysteresis = <2000>; 4670 type = "passive"; 4671 }; 4672 4673 cpu1_crit: cpu-critical { 4674 temperature = <110000>; 4675 hysteresis = <1000>; 4676 type = "critical"; 4677 }; 4678 }; 4679 }; 4680 4681 cpu2-thermal { 4682 polling-delay-passive = <0>; 4683 polling-delay = <0>; 4684 thermal-sensors = <&tsens1 3>; 4685 4686 trips { 4687 cpu2_alert0: trip-point0 { 4688 temperature = <90000>; 4689 hysteresis = <2000>; 4690 type = "passive"; 4691 }; 4692 4693 cpu2_alert1: trip-point1 { 4694 temperature = <95000>; 4695 hysteresis = <2000>; 4696 type = "passive"; 4697 }; 4698 4699 cpu2_crit: cpu-critical { 4700 temperature = <110000>; 4701 hysteresis = <1000>; 4702 type = "critical"; 4703 }; 4704 }; 4705 }; 4706 4707 cdsp0-thermal { 4708 polling-delay-passive = <10>; 4709 polling-delay = <0>; 4710 thermal-sensors = <&tsens2 4>; 4711 4712 trips { 4713 thermal-engine-config { 4714 temperature = <125000>; 4715 hysteresis = <1000>; 4716 type = "passive"; 4717 }; 4718 4719 thermal-hal-config { 4720 temperature = <125000>; 4721 hysteresis = <1000>; 4722 type = "passive"; 4723 }; 4724 4725 reset-mon-config { 4726 temperature = <115000>; 4727 hysteresis = <5000>; 4728 type = "passive"; 4729 }; 4730 4731 cdsp0_junction_config: junction-config { 4732 temperature = <95000>; 4733 hysteresis = <5000>; 4734 type = "passive"; 4735 }; 4736 }; 4737 }; 4738 4739 cdsp1-thermal { 4740 polling-delay-passive = <10>; 4741 polling-delay = <0>; 4742 thermal-sensors = <&tsens2 5>; 4743 4744 trips { 4745 thermal-engine-config { 4746 temperature = <125000>; 4747 hysteresis = <1000>; 4748 type = "passive"; 4749 }; 4750 4751 thermal-hal-config { 4752 temperature = <125000>; 4753 hysteresis = <1000>; 4754 type = "passive"; 4755 }; 4756 4757 reset-mon-config { 4758 temperature = <115000>; 4759 hysteresis = <5000>; 4760 type = "passive"; 4761 }; 4762 4763 cdsp1_junction_config: junction-config { 4764 temperature = <95000>; 4765 hysteresis = <5000>; 4766 type = "passive"; 4767 }; 4768 }; 4769 }; 4770 4771 cdsp2-thermal { 4772 polling-delay-passive = <10>; 4773 polling-delay = <0>; 4774 thermal-sensors = <&tsens2 6>; 4775 4776 trips { 4777 thermal-engine-config { 4778 temperature = <125000>; 4779 hysteresis = <1000>; 4780 type = "passive"; 4781 }; 4782 4783 thermal-hal-config { 4784 temperature = <125000>; 4785 hysteresis = <1000>; 4786 type = "passive"; 4787 }; 4788 4789 reset-mon-config { 4790 temperature = <115000>; 4791 hysteresis = <5000>; 4792 type = "passive"; 4793 }; 4794 4795 cdsp2_junction_config: junction-config { 4796 temperature = <95000>; 4797 hysteresis = <5000>; 4798 type = "passive"; 4799 }; 4800 }; 4801 }; 4802 4803 cdsp3-thermal { 4804 polling-delay-passive = <10>; 4805 polling-delay = <0>; 4806 thermal-sensors = <&tsens2 7>; 4807 4808 trips { 4809 thermal-engine-config { 4810 temperature = <125000>; 4811 hysteresis = <1000>; 4812 type = "passive"; 4813 }; 4814 4815 thermal-hal-config { 4816 temperature = <125000>; 4817 hysteresis = <1000>; 4818 type = "passive"; 4819 }; 4820 4821 reset-mon-config { 4822 temperature = <115000>; 4823 hysteresis = <5000>; 4824 type = "passive"; 4825 }; 4826 4827 cdsp3_junction_config: junction-config { 4828 temperature = <95000>; 4829 hysteresis = <5000>; 4830 type = "passive"; 4831 }; 4832 }; 4833 }; 4834 4835 video-thermal { 4836 polling-delay-passive = <0>; 4837 polling-delay = <0>; 4838 thermal-sensors = <&tsens1 8>; 4839 4840 trips { 4841 thermal-engine-config { 4842 temperature = <125000>; 4843 hysteresis = <1000>; 4844 type = "passive"; 4845 }; 4846 4847 reset-mon-config { 4848 temperature = <115000>; 4849 hysteresis = <5000>; 4850 type = "passive"; 4851 }; 4852 }; 4853 }; 4854 4855 mem-thermal { 4856 polling-delay-passive = <10>; 4857 polling-delay = <0>; 4858 thermal-sensors = <&tsens1 9>; 4859 4860 trips { 4861 thermal-engine-config { 4862 temperature = <125000>; 4863 hysteresis = <1000>; 4864 type = "passive"; 4865 }; 4866 4867 ddr_config0: ddr0-config { 4868 temperature = <90000>; 4869 hysteresis = <5000>; 4870 type = "passive"; 4871 }; 4872 4873 reset-mon-config { 4874 temperature = <115000>; 4875 hysteresis = <5000>; 4876 type = "passive"; 4877 }; 4878 }; 4879 }; 4880 4881 modem0-thermal { 4882 polling-delay-passive = <0>; 4883 polling-delay = <0>; 4884 thermal-sensors = <&tsens1 10>; 4885 4886 trips { 4887 thermal-engine-config { 4888 temperature = <125000>; 4889 hysteresis = <1000>; 4890 type = "passive"; 4891 }; 4892 4893 mdmss0_config0: mdmss0-config0 { 4894 temperature = <102000>; 4895 hysteresis = <3000>; 4896 type = "passive"; 4897 }; 4898 4899 mdmss0_config1: mdmss0-config1 { 4900 temperature = <105000>; 4901 hysteresis = <3000>; 4902 type = "passive"; 4903 }; 4904 4905 reset-mon-config { 4906 temperature = <115000>; 4907 hysteresis = <5000>; 4908 type = "passive"; 4909 }; 4910 }; 4911 }; 4912 4913 modem1-thermal { 4914 polling-delay-passive = <0>; 4915 polling-delay = <0>; 4916 thermal-sensors = <&tsens1 11>; 4917 4918 trips { 4919 thermal-engine-config { 4920 temperature = <125000>; 4921 hysteresis = <1000>; 4922 type = "passive"; 4923 }; 4924 4925 mdmss1_config0: mdmss1-config0 { 4926 temperature = <102000>; 4927 hysteresis = <3000>; 4928 type = "passive"; 4929 }; 4930 4931 mdmss1_config1: mdmss1-config1 { 4932 temperature = <105000>; 4933 hysteresis = <3000>; 4934 type = "passive"; 4935 }; 4936 4937 reset-mon-config { 4938 temperature = <115000>; 4939 hysteresis = <5000>; 4940 type = "passive"; 4941 }; 4942 }; 4943 }; 4944 4945 modem2-thermal { 4946 polling-delay-passive = <0>; 4947 polling-delay = <0>; 4948 thermal-sensors = <&tsens1 12>; 4949 4950 trips { 4951 thermal-engine-config { 4952 temperature = <125000>; 4953 hysteresis = <1000>; 4954 type = "passive"; 4955 }; 4956 4957 mdmss2_config0: mdmss2-config0 { 4958 temperature = <102000>; 4959 hysteresis = <3000>; 4960 type = "passive"; 4961 }; 4962 4963 mdmss2_config1: mdmss2-config1 { 4964 temperature = <105000>; 4965 hysteresis = <3000>; 4966 type = "passive"; 4967 }; 4968 4969 reset-mon-config { 4970 temperature = <115000>; 4971 hysteresis = <5000>; 4972 type = "passive"; 4973 }; 4974 }; 4975 }; 4976 4977 modem3-thermal { 4978 polling-delay-passive = <0>; 4979 polling-delay = <0>; 4980 thermal-sensors = <&tsens1 13>; 4981 4982 trips { 4983 thermal-engine-config { 4984 temperature = <125000>; 4985 hysteresis = <1000>; 4986 type = "passive"; 4987 }; 4988 4989 mdmss3_config0: mdmss3-config0 { 4990 temperature = <102000>; 4991 hysteresis = <3000>; 4992 type = "passive"; 4993 }; 4994 4995 mdmss3_config1: mdmss3-config1 { 4996 temperature = <105000>; 4997 hysteresis = <3000>; 4998 type = "passive"; 4999 }; 5000 5001 reset-mon-config { 5002 temperature = <115000>; 5003 hysteresis = <5000>; 5004 type = "passive"; 5005 }; 5006 }; 5007 }; 5008 5009 camera0-thermal { 5010 polling-delay-passive = <0>; 5011 polling-delay = <0>; 5012 thermal-sensors = <&tsens1 14>; 5013 5014 trips { 5015 thermal-engine-config { 5016 temperature = <125000>; 5017 hysteresis = <1000>; 5018 type = "passive"; 5019 }; 5020 5021 reset-mon-config { 5022 temperature = <115000>; 5023 hysteresis = <5000>; 5024 type = "passive"; 5025 }; 5026 }; 5027 }; 5028 5029 camera1-thermal { 5030 polling-delay-passive = <0>; 5031 polling-delay = <0>; 5032 thermal-sensors = <&tsens1 15>; 5033 5034 trips { 5035 thermal-engine-config { 5036 temperature = <125000>; 5037 hysteresis = <1000>; 5038 type = "passive"; 5039 }; 5040 5041 reset-mon-config { 5042 temperature = <115000>; 5043 hysteresis = <5000>; 5044 type = "passive"; 5045 }; 5046 }; 5047 }; 5048 5049 aoss2-thermal { 5050 polling-delay-passive = <0>; 5051 polling-delay = <0>; 5052 thermal-sensors = <&tsens2 0>; 5053 5054 trips { 5055 thermal-engine-config { 5056 temperature = <125000>; 5057 hysteresis = <1000>; 5058 type = "passive"; 5059 }; 5060 5061 reset-mon-config { 5062 temperature = <115000>; 5063 hysteresis = <5000>; 5064 type = "passive"; 5065 }; 5066 }; 5067 }; 5068 5069 gpuss-0-thermal { 5070 polling-delay-passive = <10>; 5071 polling-delay = <0>; 5072 thermal-sensors = <&tsens2 1>; 5073 5074 trips { 5075 thermal-engine-config { 5076 temperature = <125000>; 5077 hysteresis = <1000>; 5078 type = "passive"; 5079 }; 5080 5081 thermal-hal-config { 5082 temperature = <125000>; 5083 hysteresis = <1000>; 5084 type = "passive"; 5085 }; 5086 5087 reset-mon-config { 5088 temperature = <115000>; 5089 hysteresis = <5000>; 5090 type = "passive"; 5091 }; 5092 5093 gpu0_junction_config: junction-config { 5094 temperature = <95000>; 5095 hysteresis = <5000>; 5096 type = "passive"; 5097 }; 5098 }; 5099 }; 5100 5101 gpuss-1-thermal { 5102 polling-delay-passive = <10>; 5103 polling-delay = <0>; 5104 thermal-sensors = <&tsens2 2>; 5105 5106 trips { 5107 thermal-engine-config { 5108 temperature = <125000>; 5109 hysteresis = <1000>; 5110 type = "passive"; 5111 }; 5112 5113 thermal-hal-config { 5114 temperature = <125000>; 5115 hysteresis = <1000>; 5116 type = "passive"; 5117 }; 5118 5119 reset-mon-config { 5120 temperature = <115000>; 5121 hysteresis = <5000>; 5122 type = "passive"; 5123 }; 5124 5125 gpu1_junction_config: junction-config { 5126 temperature = <95000>; 5127 hysteresis = <5000>; 5128 type = "passive"; 5129 }; 5130 }; 5131 }; 5132 5133 gpuss-2-thermal { 5134 polling-delay-passive = <10>; 5135 polling-delay = <0>; 5136 thermal-sensors = <&tsens2 3>; 5137 5138 trips { 5139 thermal-engine-config { 5140 temperature = <125000>; 5141 hysteresis = <1000>; 5142 type = "passive"; 5143 }; 5144 5145 thermal-hal-config { 5146 temperature = <125000>; 5147 hysteresis = <1000>; 5148 type = "passive"; 5149 }; 5150 5151 reset-mon-config { 5152 temperature = <115000>; 5153 hysteresis = <5000>; 5154 type = "passive"; 5155 }; 5156 5157 gpu2_junction_config: junction-config { 5158 temperature = <95000>; 5159 hysteresis = <5000>; 5160 type = "passive"; 5161 }; 5162 }; 5163 }; 5164 5165 gpuss-3-thermal { 5166 polling-delay-passive = <10>; 5167 polling-delay = <0>; 5168 thermal-sensors = <&tsens2 4>; 5169 5170 trips { 5171 thermal-engine-config { 5172 temperature = <125000>; 5173 hysteresis = <1000>; 5174 type = "passive"; 5175 }; 5176 5177 thermal-hal-config { 5178 temperature = <125000>; 5179 hysteresis = <1000>; 5180 type = "passive"; 5181 }; 5182 5183 reset-mon-config { 5184 temperature = <115000>; 5185 hysteresis = <5000>; 5186 type = "passive"; 5187 }; 5188 5189 gpu3_junction_config: junction-config { 5190 temperature = <95000>; 5191 hysteresis = <5000>; 5192 type = "passive"; 5193 }; 5194 }; 5195 }; 5196 5197 gpuss-4-thermal { 5198 polling-delay-passive = <10>; 5199 polling-delay = <0>; 5200 thermal-sensors = <&tsens2 5>; 5201 5202 trips { 5203 thermal-engine-config { 5204 temperature = <125000>; 5205 hysteresis = <1000>; 5206 type = "passive"; 5207 }; 5208 5209 thermal-hal-config { 5210 temperature = <125000>; 5211 hysteresis = <1000>; 5212 type = "passive"; 5213 }; 5214 5215 reset-mon-config { 5216 temperature = <115000>; 5217 hysteresis = <5000>; 5218 type = "passive"; 5219 }; 5220 5221 gpu4_junction_config: junction-config { 5222 temperature = <95000>; 5223 hysteresis = <5000>; 5224 type = "passive"; 5225 }; 5226 }; 5227 }; 5228 5229 gpuss-5-thermal { 5230 polling-delay-passive = <10>; 5231 polling-delay = <0>; 5232 thermal-sensors = <&tsens2 6>; 5233 5234 trips { 5235 thermal-engine-config { 5236 temperature = <125000>; 5237 hysteresis = <1000>; 5238 type = "passive"; 5239 }; 5240 5241 thermal-hal-config { 5242 temperature = <125000>; 5243 hysteresis = <1000>; 5244 type = "passive"; 5245 }; 5246 5247 reset-mon-config { 5248 temperature = <115000>; 5249 hysteresis = <5000>; 5250 type = "passive"; 5251 }; 5252 5253 gpu5_junction_config: junction-config { 5254 temperature = <95000>; 5255 hysteresis = <5000>; 5256 type = "passive"; 5257 }; 5258 }; 5259 }; 5260 5261 gpuss-6-thermal { 5262 polling-delay-passive = <10>; 5263 polling-delay = <0>; 5264 thermal-sensors = <&tsens2 7>; 5265 5266 trips { 5267 thermal-engine-config { 5268 temperature = <125000>; 5269 hysteresis = <1000>; 5270 type = "passive"; 5271 }; 5272 5273 thermal-hal-config { 5274 temperature = <125000>; 5275 hysteresis = <1000>; 5276 type = "passive"; 5277 }; 5278 5279 reset-mon-config { 5280 temperature = <115000>; 5281 hysteresis = <5000>; 5282 type = "passive"; 5283 }; 5284 5285 gpu6_junction_config: junction-config { 5286 temperature = <95000>; 5287 hysteresis = <5000>; 5288 type = "passive"; 5289 }; 5290 }; 5291 }; 5292 5293 gpuss-7-thermal { 5294 polling-delay-passive = <10>; 5295 polling-delay = <0>; 5296 thermal-sensors = <&tsens2 8>; 5297 5298 trips { 5299 thermal-engine-config { 5300 temperature = <125000>; 5301 hysteresis = <1000>; 5302 type = "passive"; 5303 }; 5304 5305 thermal-hal-config { 5306 temperature = <125000>; 5307 hysteresis = <1000>; 5308 type = "passive"; 5309 }; 5310 5311 reset-mon-config { 5312 temperature = <115000>; 5313 hysteresis = <5000>; 5314 type = "passive"; 5315 }; 5316 5317 gpu7_junction_config: junction-config { 5318 temperature = <95000>; 5319 hysteresis = <5000>; 5320 type = "passive"; 5321 }; 5322 }; 5323 }; 5324 }; 5325 5326 timer { 5327 compatible = "arm,armv8-timer"; 5328 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5329 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5330 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5331 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5332 }; 5333}; 5334