1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/clock/qcom,gcc-msm8960.h> 5#include <dt-bindings/clock/qcom,lcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 model = "Qualcomm APQ8064"; 16 compatible = "qcom,apq8064"; 17 interrupt-parent = <&intc>; 18 19 reserved-memory { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 ranges; 23 24 smem_region: smem@80000000 { 25 reg = <0x80000000 0x200000>; 26 no-map; 27 }; 28 29 wcnss_mem: wcnss@8f000000 { 30 reg = <0x8f000000 0x700000>; 31 no-map; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 compatible = "qcom,krait"; 41 enable-method = "qcom,kpss-acc-v1"; 42 device_type = "cpu"; 43 reg = <0>; 44 next-level-cache = <&L2>; 45 qcom,acc = <&acc0>; 46 qcom,saw = <&saw0>; 47 cpu-idle-states = <&CPU_SPC>; 48 }; 49 50 CPU1: cpu@1 { 51 compatible = "qcom,krait"; 52 enable-method = "qcom,kpss-acc-v1"; 53 device_type = "cpu"; 54 reg = <1>; 55 next-level-cache = <&L2>; 56 qcom,acc = <&acc1>; 57 qcom,saw = <&saw1>; 58 cpu-idle-states = <&CPU_SPC>; 59 }; 60 61 CPU2: cpu@2 { 62 compatible = "qcom,krait"; 63 enable-method = "qcom,kpss-acc-v1"; 64 device_type = "cpu"; 65 reg = <2>; 66 next-level-cache = <&L2>; 67 qcom,acc = <&acc2>; 68 qcom,saw = <&saw2>; 69 cpu-idle-states = <&CPU_SPC>; 70 }; 71 72 CPU3: cpu@3 { 73 compatible = "qcom,krait"; 74 enable-method = "qcom,kpss-acc-v1"; 75 device_type = "cpu"; 76 reg = <3>; 77 next-level-cache = <&L2>; 78 qcom,acc = <&acc3>; 79 qcom,saw = <&saw3>; 80 cpu-idle-states = <&CPU_SPC>; 81 }; 82 83 L2: l2-cache { 84 compatible = "cache"; 85 cache-level = <2>; 86 cache-unified; 87 }; 88 89 idle-states { 90 CPU_SPC: spc { 91 compatible = "qcom,idle-state-spc", 92 "arm,idle-state"; 93 entry-latency-us = <400>; 94 exit-latency-us = <900>; 95 min-residency-us = <3000>; 96 }; 97 }; 98 }; 99 100 memory@0 { 101 device_type = "memory"; 102 reg = <0x0 0x0>; 103 }; 104 105 thermal-zones { 106 cpu0-thermal { 107 polling-delay-passive = <250>; 108 polling-delay = <1000>; 109 110 thermal-sensors = <&tsens 7>; 111 coefficients = <1199 0>; 112 113 trips { 114 cpu_alert0: trip0 { 115 temperature = <75000>; 116 hysteresis = <2000>; 117 type = "passive"; 118 }; 119 cpu_crit0: trip1 { 120 temperature = <110000>; 121 hysteresis = <2000>; 122 type = "critical"; 123 }; 124 }; 125 }; 126 127 cpu1-thermal { 128 polling-delay-passive = <250>; 129 polling-delay = <1000>; 130 131 thermal-sensors = <&tsens 8>; 132 coefficients = <1132 0>; 133 134 trips { 135 cpu_alert1: trip0 { 136 temperature = <75000>; 137 hysteresis = <2000>; 138 type = "passive"; 139 }; 140 cpu_crit1: trip1 { 141 temperature = <110000>; 142 hysteresis = <2000>; 143 type = "critical"; 144 }; 145 }; 146 }; 147 148 cpu2-thermal { 149 polling-delay-passive = <250>; 150 polling-delay = <1000>; 151 152 thermal-sensors = <&tsens 9>; 153 coefficients = <1199 0>; 154 155 trips { 156 cpu_alert2: trip0 { 157 temperature = <75000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 cpu_crit2: trip1 { 162 temperature = <110000>; 163 hysteresis = <2000>; 164 type = "critical"; 165 }; 166 }; 167 }; 168 169 cpu3-thermal { 170 polling-delay-passive = <250>; 171 polling-delay = <1000>; 172 173 thermal-sensors = <&tsens 10>; 174 coefficients = <1132 0>; 175 176 trips { 177 cpu_alert3: trip0 { 178 temperature = <75000>; 179 hysteresis = <2000>; 180 type = "passive"; 181 }; 182 cpu_crit3: trip1 { 183 temperature = <110000>; 184 hysteresis = <2000>; 185 type = "critical"; 186 }; 187 }; 188 }; 189 }; 190 191 cpu-pmu { 192 compatible = "qcom,krait-pmu"; 193 interrupts = <1 10 0x304>; 194 }; 195 196 clocks { 197 cxo_board: cxo_board { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <19200000>; 201 }; 202 203 pxo_board: pxo_board { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <27000000>; 207 }; 208 209 sleep_clk: sleep_clk { 210 compatible = "fixed-clock"; 211 #clock-cells = <0>; 212 clock-frequency = <32768>; 213 }; 214 }; 215 216 smem { 217 compatible = "qcom,smem"; 218 memory-region = <&smem_region>; 219 220 hwlocks = <&sfpb_mutex 3>; 221 }; 222 223 smsm { 224 compatible = "qcom,smsm"; 225 226 #address-cells = <1>; 227 #size-cells = <0>; 228 229 qcom,ipc-1 = <&l2cc 8 4>; 230 qcom,ipc-2 = <&l2cc 8 14>; 231 qcom,ipc-3 = <&l2cc 8 23>; 232 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 233 234 apps_smsm: apps@0 { 235 reg = <0>; 236 #qcom,smem-state-cells = <1>; 237 }; 238 239 modem_smsm: modem@1 { 240 reg = <1>; 241 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; 242 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 }; 246 247 q6_smsm: q6@2 { 248 reg = <2>; 249 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; 250 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 }; 254 255 wcnss_smsm: wcnss@3 { 256 reg = <3>; 257 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; 258 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 }; 262 263 dsps_smsm: dsps@4 { 264 reg = <4>; 265 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; 266 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 }; 270 }; 271 272 firmware { 273 scm { 274 compatible = "qcom,scm-apq8064", "qcom,scm"; 275 276 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 277 clock-names = "core"; 278 }; 279 }; 280 281 282 /* 283 * These channels from the ADC are simply hardware monitors. 284 * That is why the ADC is referred to as "HKADC" - HouseKeeping 285 * ADC. 286 */ 287 iio-hwmon { 288 compatible = "iio-hwmon"; 289 io-channels = <&xoadc 0x00 0x01>, /* Battery */ 290 <&xoadc 0x00 0x02>, /* DC in (charger) */ 291 <&xoadc 0x00 0x04>, /* VPH the main system voltage */ 292 <&xoadc 0x00 0x0b>, /* Die temperature */ 293 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 294 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 295 <&xoadc 0x00 0x0e>; /* Charger temperature */ 296 }; 297 298 soc: soc { 299 #address-cells = <1>; 300 #size-cells = <1>; 301 ranges; 302 compatible = "simple-bus"; 303 304 tlmm_pinmux: pinctrl@800000 { 305 compatible = "qcom,apq8064-pinctrl"; 306 reg = <0x800000 0x4000>; 307 308 gpio-controller; 309 gpio-ranges = <&tlmm_pinmux 0 0 90>; 310 #gpio-cells = <2>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 314 315 pinctrl-names = "default"; 316 pinctrl-0 = <&ps_hold>; 317 }; 318 319 sfpb_mutex: hwmutex@1200600 { 320 compatible = "qcom,sfpb-mutex"; 321 reg = <0x01200600 0x100>; 322 #hwlock-cells = <1>; 323 }; 324 325 intc: interrupt-controller@2000000 { 326 compatible = "qcom,msm-qgic2"; 327 interrupt-controller; 328 #interrupt-cells = <3>; 329 reg = <0x02000000 0x1000>, 330 <0x02002000 0x1000>; 331 }; 332 333 timer@200a000 { 334 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", 335 "qcom,msm-timer"; 336 interrupts = <1 1 0x301>, 337 <1 2 0x301>, 338 <1 3 0x301>; 339 reg = <0x0200a000 0x100>; 340 clock-frequency = <27000000>; 341 clocks = <&sleep_clk>; 342 clock-names = "sleep"; 343 cpu-offset = <0x80000>; 344 }; 345 346 acc0: clock-controller@2088000 { 347 compatible = "qcom,kpss-acc-v1"; 348 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 349 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 350 clock-names = "pll8_vote", "pxo"; 351 clock-output-names = "acpu0_aux"; 352 #clock-cells = <0>; 353 }; 354 355 acc1: clock-controller@2098000 { 356 compatible = "qcom,kpss-acc-v1"; 357 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 358 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 359 clock-names = "pll8_vote", "pxo"; 360 clock-output-names = "acpu1_aux"; 361 #clock-cells = <0>; 362 }; 363 364 acc2: clock-controller@20a8000 { 365 compatible = "qcom,kpss-acc-v1"; 366 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 367 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 368 clock-names = "pll8_vote", "pxo"; 369 clock-output-names = "acpu2_aux"; 370 #clock-cells = <0>; 371 }; 372 373 acc3: clock-controller@20b8000 { 374 compatible = "qcom,kpss-acc-v1"; 375 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 376 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 377 clock-names = "pll8_vote", "pxo"; 378 clock-output-names = "acpu3_aux"; 379 #clock-cells = <0>; 380 }; 381 382 saw0: power-controller@2089000 { 383 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 384 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 385 regulator; 386 }; 387 388 saw1: power-controller@2099000 { 389 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 390 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 391 regulator; 392 }; 393 394 saw2: power-controller@20a9000 { 395 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 396 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 397 regulator; 398 }; 399 400 saw3: power-controller@20b9000 { 401 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 402 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 403 regulator; 404 }; 405 406 sps_sic_non_secure: sps-sic-non-secure@12100000 { 407 compatible = "syscon"; 408 reg = <0x12100000 0x10000>; 409 }; 410 411 gsbi1: gsbi@12440000 { 412 status = "disabled"; 413 compatible = "qcom,gsbi-v1.0.0"; 414 cell-index = <1>; 415 reg = <0x12440000 0x100>; 416 clocks = <&gcc GSBI1_H_CLK>; 417 clock-names = "iface"; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges; 421 422 syscon-tcsr = <&tcsr>; 423 424 gsbi1_serial: serial@12450000 { 425 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 426 reg = <0x12450000 0x100>, 427 <0x12400000 0x03>; 428 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 430 clock-names = "core", "iface"; 431 status = "disabled"; 432 }; 433 434 gsbi1_i2c: i2c@12460000 { 435 compatible = "qcom,i2c-qup-v1.1.1"; 436 pinctrl-0 = <&i2c1_pins>; 437 pinctrl-1 = <&i2c1_pins_sleep>; 438 pinctrl-names = "default", "sleep"; 439 reg = <0x12460000 0x1000>; 440 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 442 clock-names = "core", "iface"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 }; 449 450 gsbi2: gsbi@12480000 { 451 status = "disabled"; 452 compatible = "qcom,gsbi-v1.0.0"; 453 cell-index = <2>; 454 reg = <0x12480000 0x100>; 455 clocks = <&gcc GSBI2_H_CLK>; 456 clock-names = "iface"; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 ranges; 460 461 syscon-tcsr = <&tcsr>; 462 463 gsbi2_i2c: i2c@124a0000 { 464 compatible = "qcom,i2c-qup-v1.1.1"; 465 reg = <0x124a0000 0x1000>; 466 pinctrl-0 = <&i2c2_pins>; 467 pinctrl-1 = <&i2c2_pins_sleep>; 468 pinctrl-names = "default", "sleep"; 469 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 471 clock-names = "core", "iface"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 }; 477 478 gsbi3: gsbi@16200000 { 479 status = "disabled"; 480 compatible = "qcom,gsbi-v1.0.0"; 481 cell-index = <3>; 482 reg = <0x16200000 0x100>; 483 clocks = <&gcc GSBI3_H_CLK>; 484 clock-names = "iface"; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 ranges; 488 gsbi3_i2c: i2c@16280000 { 489 compatible = "qcom,i2c-qup-v1.1.1"; 490 pinctrl-0 = <&i2c3_pins>; 491 pinctrl-1 = <&i2c3_pins_sleep>; 492 pinctrl-names = "default", "sleep"; 493 reg = <0x16280000 0x1000>; 494 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&gcc GSBI3_QUP_CLK>, 496 <&gcc GSBI3_H_CLK>; 497 clock-names = "core", "iface"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 status = "disabled"; 501 }; 502 }; 503 504 gsbi4: gsbi@16300000 { 505 status = "disabled"; 506 compatible = "qcom,gsbi-v1.0.0"; 507 cell-index = <4>; 508 reg = <0x16300000 0x03>; 509 clocks = <&gcc GSBI4_H_CLK>; 510 clock-names = "iface"; 511 #address-cells = <1>; 512 #size-cells = <1>; 513 ranges; 514 515 gsbi4_serial: serial@16340000 { 516 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 517 reg = <0x16340000 0x100>, 518 <0x16300000 0x3>; 519 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 520 pinctrl-0 = <&gsbi4_uart_pin_a>; 521 pinctrl-names = "default"; 522 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 523 clock-names = "core", "iface"; 524 status = "disabled"; 525 }; 526 527 gsbi4_i2c: i2c@16380000 { 528 compatible = "qcom,i2c-qup-v1.1.1"; 529 pinctrl-0 = <&i2c4_pins>; 530 pinctrl-1 = <&i2c4_pins_sleep>; 531 pinctrl-names = "default", "sleep"; 532 reg = <0x16380000 0x1000>; 533 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&gcc GSBI4_QUP_CLK>, 535 <&gcc GSBI4_H_CLK>; 536 clock-names = "core", "iface"; 537 status = "disabled"; 538 }; 539 }; 540 541 gsbi5: gsbi@1a200000 { 542 status = "disabled"; 543 compatible = "qcom,gsbi-v1.0.0"; 544 cell-index = <5>; 545 reg = <0x1a200000 0x03>; 546 clocks = <&gcc GSBI5_H_CLK>; 547 clock-names = "iface"; 548 #address-cells = <1>; 549 #size-cells = <1>; 550 ranges; 551 552 gsbi5_serial: serial@1a240000 { 553 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 554 reg = <0x1a240000 0x100>, 555 <0x1a200000 0x03>; 556 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 558 clock-names = "core", "iface"; 559 status = "disabled"; 560 }; 561 562 gsbi5_spi: spi@1a280000 { 563 compatible = "qcom,spi-qup-v1.1.1"; 564 reg = <0x1a280000 0x1000>; 565 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 566 pinctrl-0 = <&spi5_default>; 567 pinctrl-1 = <&spi5_sleep>; 568 pinctrl-names = "default", "sleep"; 569 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 570 clock-names = "core", "iface"; 571 status = "disabled"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 }; 575 }; 576 577 gsbi6: gsbi@16500000 { 578 status = "disabled"; 579 compatible = "qcom,gsbi-v1.0.0"; 580 cell-index = <6>; 581 reg = <0x16500000 0x03>; 582 clocks = <&gcc GSBI6_H_CLK>; 583 clock-names = "iface"; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 ranges; 587 588 gsbi6_serial: serial@16540000 { 589 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 590 reg = <0x16540000 0x100>, 591 <0x16500000 0x03>; 592 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 594 clock-names = "core", "iface"; 595 status = "disabled"; 596 }; 597 598 gsbi6_i2c: i2c@16580000 { 599 compatible = "qcom,i2c-qup-v1.1.1"; 600 pinctrl-0 = <&i2c6_pins>; 601 pinctrl-1 = <&i2c6_pins_sleep>; 602 pinctrl-names = "default", "sleep"; 603 reg = <0x16580000 0x1000>; 604 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&gcc GSBI6_QUP_CLK>, 606 <&gcc GSBI6_H_CLK>; 607 clock-names = "core", "iface"; 608 status = "disabled"; 609 }; 610 }; 611 612 gsbi7: gsbi@16600000 { 613 status = "disabled"; 614 compatible = "qcom,gsbi-v1.0.0"; 615 cell-index = <7>; 616 reg = <0x16600000 0x100>; 617 clocks = <&gcc GSBI7_H_CLK>; 618 clock-names = "iface"; 619 #address-cells = <1>; 620 #size-cells = <1>; 621 ranges; 622 syscon-tcsr = <&tcsr>; 623 624 gsbi7_serial: serial@16640000 { 625 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 626 reg = <0x16640000 0x1000>, 627 <0x16600000 0x1000>; 628 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 630 clock-names = "core", "iface"; 631 status = "disabled"; 632 }; 633 634 gsbi7_i2c: i2c@16680000 { 635 compatible = "qcom,i2c-qup-v1.1.1"; 636 pinctrl-0 = <&i2c7_pins>; 637 pinctrl-1 = <&i2c7_pins_sleep>; 638 pinctrl-names = "default", "sleep"; 639 reg = <0x16680000 0x1000>; 640 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&gcc GSBI7_QUP_CLK>, 642 <&gcc GSBI7_H_CLK>; 643 clock-names = "core", "iface"; 644 status = "disabled"; 645 }; 646 }; 647 648 rng@1a500000 { 649 compatible = "qcom,prng"; 650 reg = <0x1a500000 0x200>; 651 clocks = <&gcc PRNG_CLK>; 652 clock-names = "core"; 653 }; 654 655 ssbi@c00000 { 656 compatible = "qcom,ssbi"; 657 reg = <0x00c00000 0x1000>; 658 qcom,controller-type = "pmic-arbiter"; 659 660 pm8821: pmic { 661 compatible = "qcom,pm8821"; 662 interrupt-parent = <&tlmm_pinmux>; 663 interrupts = <76 IRQ_TYPE_LEVEL_LOW>; 664 #interrupt-cells = <2>; 665 interrupt-controller; 666 #address-cells = <1>; 667 #size-cells = <0>; 668 669 pm8821_mpps: mpps@50 { 670 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; 671 reg = <0x50>; 672 interrupt-controller; 673 #interrupt-cells = <2>; 674 gpio-controller; 675 #gpio-cells = <2>; 676 gpio-ranges = <&pm8821_mpps 0 0 4>; 677 }; 678 }; 679 }; 680 681 ssbi@500000 { 682 compatible = "qcom,ssbi"; 683 reg = <0x00500000 0x1000>; 684 qcom,controller-type = "pmic-arbiter"; 685 686 pmicintc: pmic { 687 compatible = "qcom,pm8921"; 688 interrupt-parent = <&tlmm_pinmux>; 689 interrupts = <74 8>; 690 #interrupt-cells = <2>; 691 interrupt-controller; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 695 pm8921_gpio: gpio@150 { 696 697 compatible = "qcom,pm8921-gpio", 698 "qcom,ssbi-gpio"; 699 reg = <0x150>; 700 interrupt-controller; 701 #interrupt-cells = <2>; 702 gpio-controller; 703 gpio-ranges = <&pm8921_gpio 0 0 44>; 704 #gpio-cells = <2>; 705 706 }; 707 708 pm8921_mpps: mpps@50 { 709 compatible = "qcom,pm8921-mpp", 710 "qcom,ssbi-mpp"; 711 reg = <0x50>; 712 gpio-controller; 713 #gpio-cells = <2>; 714 gpio-ranges = <&pm8921_mpps 0 0 12>; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 719 rtc@11d { 720 compatible = "qcom,pm8921-rtc"; 721 interrupt-parent = <&pmicintc>; 722 interrupts = <39 1>; 723 reg = <0x11d>; 724 allow-set-time; 725 }; 726 727 pwrkey@1c { 728 compatible = "qcom,pm8921-pwrkey"; 729 reg = <0x1c>; 730 interrupt-parent = <&pmicintc>; 731 interrupts = <50 1>, <51 1>; 732 debounce = <15625>; 733 pull-up; 734 }; 735 736 xoadc: xoadc@197 { 737 compatible = "qcom,pm8921-adc"; 738 reg = <0x197>; 739 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; 740 #address-cells = <2>; 741 #size-cells = <0>; 742 #io-channel-cells = <2>; 743 744 vcoin: adc-channel@0 { 745 reg = <0x00 0x00>; 746 }; 747 vbat: adc-channel@1 { 748 reg = <0x00 0x01>; 749 }; 750 dcin: adc-channel@2 { 751 reg = <0x00 0x02>; 752 }; 753 vph_pwr: adc-channel@4 { 754 reg = <0x00 0x04>; 755 }; 756 batt_therm: adc-channel@8 { 757 reg = <0x00 0x08>; 758 }; 759 batt_id: adc-channel@9 { 760 reg = <0x00 0x09>; 761 }; 762 usb_vbus: adc-channel@a { 763 reg = <0x00 0x0a>; 764 }; 765 die_temp: adc-channel@b { 766 reg = <0x00 0x0b>; 767 }; 768 ref_625mv: adc-channel@c { 769 reg = <0x00 0x0c>; 770 }; 771 ref_1250mv: adc-channel@d { 772 reg = <0x00 0x0d>; 773 }; 774 chg_temp: adc-channel@e { 775 reg = <0x00 0x0e>; 776 }; 777 ref_muxoff: adc-channel@f { 778 reg = <0x00 0x0f>; 779 }; 780 }; 781 }; 782 }; 783 784 qfprom: qfprom@700000 { 785 compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; 786 reg = <0x00700000 0x1000>; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 ranges; 790 tsens_calib: calib@404 { 791 reg = <0x404 0x10>; 792 }; 793 tsens_backup: backup_calib@414 { 794 reg = <0x414 0x10>; 795 }; 796 }; 797 798 gcc: clock-controller@900000 { 799 compatible = "qcom,gcc-apq8064", "syscon"; 800 reg = <0x00900000 0x4000>; 801 #clock-cells = <1>; 802 #power-domain-cells = <1>; 803 #reset-cells = <1>; 804 clocks = <&cxo_board>, 805 <&pxo_board>, 806 <&lcc PLL4>; 807 clock-names = "cxo", "pxo", "pll4"; 808 809 tsens: thermal-sensor { 810 compatible = "qcom,msm8960-tsens"; 811 812 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 813 nvmem-cell-names = "calib", "calib_backup"; 814 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-names = "uplow"; 816 817 #qcom,sensors = <11>; 818 #thermal-sensor-cells = <1>; 819 }; 820 }; 821 822 lcc: clock-controller@28000000 { 823 compatible = "qcom,lcc-apq8064"; 824 reg = <0x28000000 0x1000>; 825 #clock-cells = <1>; 826 #reset-cells = <1>; 827 clocks = <&pxo_board>, 828 <&gcc PLL4_VOTE>, 829 <0>, 830 <0>, <0>, 831 <0>, <0>, 832 <0>; 833 clock-names = "pxo", 834 "pll4_vote", 835 "mi2s_codec_clk", 836 "codec_i2s_mic_codec_clk", 837 "spare_i2s_mic_codec_clk", 838 "codec_i2s_spkr_codec_clk", 839 "spare_i2s_spkr_codec_clk", 840 "pcm_codec_clk"; 841 }; 842 843 mmcc: clock-controller@4000000 { 844 compatible = "qcom,mmcc-apq8064"; 845 reg = <0x4000000 0x1000>; 846 #clock-cells = <1>; 847 #power-domain-cells = <1>; 848 #reset-cells = <1>; 849 clocks = <&pxo_board>, 850 <&gcc PLL3>, 851 <&gcc PLL8_VOTE>, 852 <&dsi0_phy 1>, 853 <&dsi0_phy 0>, 854 <&dsi1_phy 1>, 855 <&dsi1_phy 0>, 856 <&hdmi_phy>; 857 clock-names = "pxo", 858 "pll3", 859 "pll8_vote", 860 "dsi1pll", 861 "dsi1pllbyte", 862 "dsi2pll", 863 "dsi2pllbyte", 864 "hdmipll"; 865 }; 866 867 l2cc: clock-controller@2011000 { 868 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; 869 reg = <0x2011000 0x1000>; 870 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 871 clock-names = "pll8_vote", "pxo"; 872 #clock-cells = <0>; 873 }; 874 875 rpm: rpm@108000 { 876 compatible = "qcom,rpm-apq8064"; 877 reg = <0x108000 0x1000>; 878 qcom,ipc = <&l2cc 0x8 2>; 879 880 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 881 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 882 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 883 interrupt-names = "ack", "err", "wakeup"; 884 885 rpmcc: clock-controller { 886 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 887 #clock-cells = <1>; 888 clocks = <&pxo_board>, <&cxo_board>; 889 clock-names = "pxo", "cxo"; 890 }; 891 892 regulators { 893 compatible = "qcom,rpm-pm8921-regulators"; 894 895 pm8921_s1: s1 {}; 896 pm8921_s2: s2 {}; 897 pm8921_s3: s3 {}; 898 pm8921_s4: s4 {}; 899 pm8921_s7: s7 {}; 900 pm8921_s8: s8 {}; 901 902 pm8921_l1: l1 {}; 903 pm8921_l2: l2 {}; 904 pm8921_l3: l3 {}; 905 pm8921_l4: l4 {}; 906 pm8921_l5: l5 {}; 907 pm8921_l6: l6 {}; 908 pm8921_l7: l7 {}; 909 pm8921_l8: l8 {}; 910 pm8921_l9: l9 {}; 911 pm8921_l10: l10 {}; 912 pm8921_l11: l11 {}; 913 pm8921_l12: l12 {}; 914 pm8921_l14: l14 {}; 915 pm8921_l15: l15 {}; 916 pm8921_l16: l16 {}; 917 pm8921_l17: l17 {}; 918 pm8921_l18: l18 {}; 919 pm8921_l21: l21 {}; 920 pm8921_l22: l22 {}; 921 pm8921_l23: l23 {}; 922 pm8921_l24: l24 {}; 923 pm8921_l25: l25 {}; 924 pm8921_l26: l26 {}; 925 pm8921_l27: l27 {}; 926 pm8921_l28: l28 {}; 927 pm8921_l29: l29 {}; 928 929 pm8921_lvs1: lvs1 {}; 930 pm8921_lvs2: lvs2 {}; 931 pm8921_lvs3: lvs3 {}; 932 pm8921_lvs4: lvs4 {}; 933 pm8921_lvs5: lvs5 {}; 934 pm8921_lvs6: lvs6 {}; 935 pm8921_lvs7: lvs7 {}; 936 937 pm8921_usb_switch: usb-switch {}; 938 939 pm8921_hdmi_switch: hdmi-switch { 940 bias-pull-down; 941 }; 942 943 pm8921_ncp: ncp {}; 944 }; 945 }; 946 947 usb1: usb@12500000 { 948 compatible = "qcom,ci-hdrc"; 949 reg = <0x12500000 0x200>, 950 <0x12500200 0x200>; 951 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 952 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 953 clock-names = "core", "iface"; 954 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 955 assigned-clock-rates = <60000000>; 956 resets = <&gcc USB_HS1_RESET>; 957 reset-names = "core"; 958 phy_type = "ulpi"; 959 ahb-burst-config = <0>; 960 phys = <&usb_hs1_phy>; 961 phy-names = "usb-phy"; 962 status = "disabled"; 963 #reset-cells = <1>; 964 965 ulpi { 966 usb_hs1_phy: phy { 967 compatible = "qcom,usb-hs-phy-apq8064", 968 "qcom,usb-hs-phy"; 969 clocks = <&sleep_clk>, <&cxo_board>; 970 clock-names = "sleep", "ref"; 971 resets = <&usb1 0>; 972 reset-names = "por"; 973 #phy-cells = <0>; 974 }; 975 }; 976 }; 977 978 usb3: usb@12520000 { 979 compatible = "qcom,ci-hdrc"; 980 reg = <0x12520000 0x200>, 981 <0x12520200 0x200>; 982 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 984 clock-names = "core", "iface"; 985 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 986 assigned-clock-rates = <60000000>; 987 resets = <&gcc USB_HS3_RESET>; 988 reset-names = "core"; 989 phy_type = "ulpi"; 990 ahb-burst-config = <0>; 991 phys = <&usb_hs3_phy>; 992 phy-names = "usb-phy"; 993 status = "disabled"; 994 #reset-cells = <1>; 995 996 ulpi { 997 usb_hs3_phy: phy { 998 compatible = "qcom,usb-hs-phy-apq8064", 999 "qcom,usb-hs-phy"; 1000 #phy-cells = <0>; 1001 clocks = <&sleep_clk>, <&cxo_board>; 1002 clock-names = "sleep", "ref"; 1003 resets = <&usb3 0>; 1004 reset-names = "por"; 1005 }; 1006 }; 1007 }; 1008 1009 usb4: usb@12530000 { 1010 compatible = "qcom,ci-hdrc"; 1011 reg = <0x12530000 0x200>, 1012 <0x12530200 0x200>; 1013 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 1015 clock-names = "core", "iface"; 1016 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 1017 assigned-clock-rates = <60000000>; 1018 resets = <&gcc USB_HS4_RESET>; 1019 reset-names = "core"; 1020 phy_type = "ulpi"; 1021 ahb-burst-config = <0>; 1022 phys = <&usb_hs4_phy>; 1023 phy-names = "usb-phy"; 1024 status = "disabled"; 1025 #reset-cells = <1>; 1026 1027 ulpi { 1028 usb_hs4_phy: phy { 1029 compatible = "qcom,usb-hs-phy-apq8064", 1030 "qcom,usb-hs-phy"; 1031 #phy-cells = <0>; 1032 clocks = <&sleep_clk>, <&cxo_board>; 1033 clock-names = "sleep", "ref"; 1034 resets = <&usb4 0>; 1035 reset-names = "por"; 1036 }; 1037 }; 1038 }; 1039 1040 sata_phy0: phy@1b400000 { 1041 compatible = "qcom,apq8064-sata-phy"; 1042 status = "disabled"; 1043 reg = <0x1b400000 0x200>; 1044 reg-names = "phy_mem"; 1045 clocks = <&gcc SATA_PHY_CFG_CLK>; 1046 clock-names = "cfg"; 1047 #phy-cells = <0>; 1048 }; 1049 1050 sata0: sata@29000000 { 1051 compatible = "qcom,apq8064-ahci", "generic-ahci"; 1052 status = "disabled"; 1053 reg = <0x29000000 0x180>; 1054 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1055 1056 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1057 <&gcc SATA_H_CLK>, 1058 <&gcc SATA_A_CLK>, 1059 <&gcc SATA_RXOOB_CLK>, 1060 <&gcc SATA_PMALIVE_CLK>; 1061 clock-names = "slave_iface", 1062 "iface", 1063 "bus", 1064 "rxoob", 1065 "core_pmalive"; 1066 1067 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1068 <&gcc SATA_PMALIVE_CLK>; 1069 assigned-clock-rates = <100000000>, <100000000>; 1070 1071 phys = <&sata_phy0>; 1072 phy-names = "sata-phy"; 1073 ports-implemented = <0x1>; 1074 }; 1075 1076 sdcc3: mmc@12180000 { 1077 compatible = "arm,pl18x", "arm,primecell"; 1078 arm,primecell-periphid = <0x00051180>; 1079 status = "disabled"; 1080 reg = <0x12180000 0x2000>; 1081 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1083 clock-names = "mclk", "apb_pclk"; 1084 bus-width = <4>; 1085 cap-sd-highspeed; 1086 cap-mmc-highspeed; 1087 max-frequency = <192000000>; 1088 no-1-8-v; 1089 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1090 dma-names = "tx", "rx"; 1091 }; 1092 1093 sdcc3bam: dma-controller@12182000 { 1094 compatible = "qcom,bam-v1.3.0"; 1095 reg = <0x12182000 0x8000>; 1096 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&gcc SDC3_H_CLK>; 1098 clock-names = "bam_clk"; 1099 #dma-cells = <1>; 1100 qcom,ee = <0>; 1101 }; 1102 1103 sdcc4: mmc@121c0000 { 1104 compatible = "arm,pl18x", "arm,primecell"; 1105 arm,primecell-periphid = <0x00051180>; 1106 status = "disabled"; 1107 reg = <0x121c0000 0x2000>; 1108 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1110 clock-names = "mclk", "apb_pclk"; 1111 bus-width = <4>; 1112 cap-sd-highspeed; 1113 cap-mmc-highspeed; 1114 max-frequency = <48000000>; 1115 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 1116 dma-names = "tx", "rx"; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&sdc4_gpios>; 1119 }; 1120 1121 sdcc4bam: dma-controller@121c2000 { 1122 compatible = "qcom,bam-v1.3.0"; 1123 reg = <0x121c2000 0x8000>; 1124 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&gcc SDC4_H_CLK>; 1126 clock-names = "bam_clk"; 1127 #dma-cells = <1>; 1128 qcom,ee = <0>; 1129 }; 1130 1131 sdcc1: mmc@12400000 { 1132 status = "disabled"; 1133 compatible = "arm,pl18x", "arm,primecell"; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&sdcc1_pins>; 1136 arm,primecell-periphid = <0x00051180>; 1137 reg = <0x12400000 0x2000>; 1138 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1139 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1140 clock-names = "mclk", "apb_pclk"; 1141 bus-width = <8>; 1142 max-frequency = <96000000>; 1143 non-removable; 1144 cap-sd-highspeed; 1145 cap-mmc-highspeed; 1146 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1147 dma-names = "tx", "rx"; 1148 }; 1149 1150 sdcc1bam: dma-controller@12402000 { 1151 compatible = "qcom,bam-v1.3.0"; 1152 reg = <0x12402000 0x8000>; 1153 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&gcc SDC1_H_CLK>; 1155 clock-names = "bam_clk"; 1156 #dma-cells = <1>; 1157 qcom,ee = <0>; 1158 }; 1159 1160 tcsr: syscon@1a400000 { 1161 compatible = "qcom,tcsr-apq8064", "syscon"; 1162 reg = <0x1a400000 0x100>; 1163 }; 1164 1165 gpu: adreno-3xx@4300000 { 1166 compatible = "qcom,adreno-320.2", "qcom,adreno"; 1167 reg = <0x04300000 0x20000>; 1168 reg-names = "kgsl_3d0_reg_memory"; 1169 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1170 interrupt-names = "kgsl_3d0_irq"; 1171 clock-names = 1172 "core", 1173 "iface", 1174 "mem", 1175 "mem_iface"; 1176 clocks = 1177 <&mmcc GFX3D_CLK>, 1178 <&mmcc GFX3D_AHB_CLK>, 1179 <&mmcc GFX3D_AXI_CLK>, 1180 <&mmcc MMSS_IMEM_AHB_CLK>; 1181 1182 iommus = <&gfx3d 0 1183 &gfx3d 1 1184 &gfx3d 2 1185 &gfx3d 3 1186 &gfx3d 4 1187 &gfx3d 5 1188 &gfx3d 6 1189 &gfx3d 7 1190 &gfx3d 8 1191 &gfx3d 9 1192 &gfx3d 10 1193 &gfx3d 11 1194 &gfx3d 12 1195 &gfx3d 13 1196 &gfx3d 14 1197 &gfx3d 15 1198 &gfx3d 16 1199 &gfx3d 17 1200 &gfx3d 18 1201 &gfx3d 19 1202 &gfx3d 20 1203 &gfx3d 21 1204 &gfx3d 22 1205 &gfx3d 23 1206 &gfx3d 24 1207 &gfx3d 25 1208 &gfx3d 26 1209 &gfx3d 27 1210 &gfx3d 28 1211 &gfx3d 29 1212 &gfx3d 30 1213 &gfx3d 31 1214 &gfx3d1 0 1215 &gfx3d1 1 1216 &gfx3d1 2 1217 &gfx3d1 3 1218 &gfx3d1 4 1219 &gfx3d1 5 1220 &gfx3d1 6 1221 &gfx3d1 7 1222 &gfx3d1 8 1223 &gfx3d1 9 1224 &gfx3d1 10 1225 &gfx3d1 11 1226 &gfx3d1 12 1227 &gfx3d1 13 1228 &gfx3d1 14 1229 &gfx3d1 15 1230 &gfx3d1 16 1231 &gfx3d1 17 1232 &gfx3d1 18 1233 &gfx3d1 19 1234 &gfx3d1 20 1235 &gfx3d1 21 1236 &gfx3d1 22 1237 &gfx3d1 23 1238 &gfx3d1 24 1239 &gfx3d1 25 1240 &gfx3d1 26 1241 &gfx3d1 27 1242 &gfx3d1 28 1243 &gfx3d1 29 1244 &gfx3d1 30 1245 &gfx3d1 31>; 1246 1247 operating-points-v2 = <&gpu_opp_table>; 1248 1249 gpu_opp_table: opp-table { 1250 compatible = "operating-points-v2"; 1251 1252 opp-450000000 { 1253 opp-hz = /bits/ 64 <450000000>; 1254 }; 1255 1256 opp-27000000 { 1257 opp-hz = /bits/ 64 <27000000>; 1258 }; 1259 }; 1260 }; 1261 1262 mmss_sfpb: syscon@5700000 { 1263 compatible = "syscon"; 1264 reg = <0x5700000 0x70>; 1265 }; 1266 1267 dsi0: dsi@4700000 { 1268 compatible = "qcom,apq8064-dsi-ctrl", 1269 "qcom,mdss-dsi-ctrl"; 1270 label = "MDSS DSI CTRL->0"; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1274 reg = <0x04700000 0x200>; 1275 reg-names = "dsi_ctrl"; 1276 1277 clocks = <&mmcc DSI_M_AHB_CLK>, 1278 <&mmcc DSI_S_AHB_CLK>, 1279 <&mmcc AMP_AHB_CLK>, 1280 <&mmcc DSI_CLK>, 1281 <&mmcc DSI1_BYTE_CLK>, 1282 <&mmcc DSI_PIXEL_CLK>, 1283 <&mmcc DSI1_ESC_CLK>; 1284 clock-names = "iface", "bus", "core_mmss", 1285 "src", "byte", "pixel", 1286 "core"; 1287 1288 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1289 <&mmcc DSI1_ESC_SRC>, 1290 <&mmcc DSI_SRC>, 1291 <&mmcc DSI_PIXEL_SRC>; 1292 assigned-clock-parents = <&dsi0_phy 0>, 1293 <&dsi0_phy 0>, 1294 <&dsi0_phy 1>, 1295 <&dsi0_phy 1>; 1296 syscon-sfpb = <&mmss_sfpb>; 1297 phys = <&dsi0_phy>; 1298 status = "disabled"; 1299 1300 ports { 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 port@0 { 1305 reg = <0>; 1306 dsi0_in: endpoint { 1307 }; 1308 }; 1309 1310 port@1 { 1311 reg = <1>; 1312 dsi0_out: endpoint { 1313 }; 1314 }; 1315 }; 1316 }; 1317 1318 1319 dsi0_phy: phy@4700200 { 1320 compatible = "qcom,dsi-phy-28nm-8960"; 1321 #clock-cells = <1>; 1322 #phy-cells = <0>; 1323 1324 reg = <0x04700200 0x100>, 1325 <0x04700300 0x200>, 1326 <0x04700500 0x5c>; 1327 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1328 clock-names = "iface", "ref"; 1329 clocks = <&mmcc DSI_M_AHB_CLK>, 1330 <&pxo_board>; 1331 status = "disabled"; 1332 }; 1333 1334 dsi1: dsi@5800000 { 1335 compatible = "qcom,mdss-dsi-ctrl"; 1336 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1337 reg = <0x05800000 0x200>; 1338 reg-names = "dsi_ctrl"; 1339 1340 clocks = <&mmcc DSI2_M_AHB_CLK>, 1341 <&mmcc DSI2_S_AHB_CLK>, 1342 <&mmcc AMP_AHB_CLK>, 1343 <&mmcc DSI2_CLK>, 1344 <&mmcc DSI2_BYTE_CLK>, 1345 <&mmcc DSI2_PIXEL_CLK>, 1346 <&mmcc DSI2_ESC_CLK>; 1347 clock-names = "iface", 1348 "bus", 1349 "core_mmss", 1350 "src", 1351 "byte", 1352 "pixel", 1353 "core"; 1354 1355 assigned-clocks = <&mmcc DSI2_BYTE_SRC>, 1356 <&mmcc DSI2_ESC_SRC>, 1357 <&mmcc DSI2_SRC>, 1358 <&mmcc DSI2_PIXEL_SRC>; 1359 assigned-clock-parents = <&dsi1_phy 0>, 1360 <&dsi1_phy 0>, 1361 <&dsi1_phy 1>, 1362 <&dsi1_phy 1>; 1363 1364 syscon-sfpb = <&mmss_sfpb>; 1365 phys = <&dsi1_phy>; 1366 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 1370 status = "disabled"; 1371 1372 ports { 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 1376 port@0 { 1377 reg = <0>; 1378 dsi1_in: endpoint { 1379 }; 1380 }; 1381 1382 port@1 { 1383 reg = <1>; 1384 dsi1_out: endpoint { 1385 }; 1386 }; 1387 }; 1388 }; 1389 1390 1391 dsi1_phy: dsi-phy@5800200 { 1392 compatible = "qcom,dsi-phy-28nm-8960"; 1393 reg = <0x05800200 0x100>, 1394 <0x05800300 0x200>, 1395 <0x05800500 0x5c>; 1396 reg-names = "dsi_pll", 1397 "dsi_phy", 1398 "dsi_phy_regulator"; 1399 clock-names = "iface", 1400 "ref"; 1401 clocks = <&mmcc DSI2_M_AHB_CLK>, 1402 <&pxo_board>; 1403 #clock-cells = <1>; 1404 #phy-cells = <0>; 1405 1406 status = "disabled"; 1407 }; 1408 1409 mdp_port0: iommu@7500000 { 1410 compatible = "qcom,apq8064-iommu"; 1411 #iommu-cells = <1>; 1412 clock-names = 1413 "smmu_pclk", 1414 "iommu_clk"; 1415 clocks = 1416 <&mmcc SMMU_AHB_CLK>, 1417 <&mmcc MDP_AXI_CLK>; 1418 reg = <0x07500000 0x100000>; 1419 interrupts = 1420 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1422 qcom,ncb = <2>; 1423 }; 1424 1425 mdp_port1: iommu@7600000 { 1426 compatible = "qcom,apq8064-iommu"; 1427 #iommu-cells = <1>; 1428 clock-names = 1429 "smmu_pclk", 1430 "iommu_clk"; 1431 clocks = 1432 <&mmcc SMMU_AHB_CLK>, 1433 <&mmcc MDP_AXI_CLK>; 1434 reg = <0x07600000 0x100000>; 1435 interrupts = 1436 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1438 qcom,ncb = <2>; 1439 }; 1440 1441 gfx3d: iommu@7c00000 { 1442 compatible = "qcom,apq8064-iommu"; 1443 #iommu-cells = <1>; 1444 clock-names = 1445 "smmu_pclk", 1446 "iommu_clk"; 1447 clocks = 1448 <&mmcc SMMU_AHB_CLK>, 1449 <&mmcc GFX3D_AXI_CLK>; 1450 reg = <0x07c00000 0x100000>; 1451 interrupts = 1452 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1454 qcom,ncb = <3>; 1455 }; 1456 1457 gfx3d1: iommu@7d00000 { 1458 compatible = "qcom,apq8064-iommu"; 1459 #iommu-cells = <1>; 1460 clock-names = 1461 "smmu_pclk", 1462 "iommu_clk"; 1463 clocks = 1464 <&mmcc SMMU_AHB_CLK>, 1465 <&mmcc GFX3D_AXI_CLK>; 1466 reg = <0x07d00000 0x100000>; 1467 interrupts = 1468 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1470 qcom,ncb = <3>; 1471 }; 1472 1473 pcie: pci@1b500000 { 1474 compatible = "qcom,pcie-apq8064"; 1475 reg = <0x1b500000 0x1000>, 1476 <0x1b502000 0x80>, 1477 <0x1b600000 0x100>, 1478 <0x0ff00000 0x100000>; 1479 reg-names = "dbi", "elbi", "parf", "config"; 1480 device_type = "pci"; 1481 linux,pci-domain = <0>; 1482 bus-range = <0x00 0xff>; 1483 num-lanes = <1>; 1484 #address-cells = <3>; 1485 #size-cells = <2>; 1486 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ 1487 <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ 1488 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1489 interrupt-names = "msi"; 1490 #interrupt-cells = <1>; 1491 interrupt-map-mask = <0 0 0 0x7>; 1492 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1493 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1494 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1495 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1496 clocks = <&gcc PCIE_A_CLK>, 1497 <&gcc PCIE_H_CLK>, 1498 <&gcc PCIE_PHY_REF_CLK>; 1499 clock-names = "core", "iface", "phy"; 1500 resets = <&gcc PCIE_ACLK_RESET>, 1501 <&gcc PCIE_HCLK_RESET>, 1502 <&gcc PCIE_POR_RESET>, 1503 <&gcc PCIE_PCI_RESET>, 1504 <&gcc PCIE_PHY_RESET>; 1505 reset-names = "axi", "ahb", "por", "pci", "phy"; 1506 status = "disabled"; 1507 }; 1508 1509 hdmi: hdmi-tx@4a00000 { 1510 compatible = "qcom,hdmi-tx-8960"; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&hdmi_pinctrl>; 1513 reg = <0x04a00000 0x2f0>; 1514 reg-names = "core_physical"; 1515 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&mmcc HDMI_APP_CLK>, 1517 <&mmcc HDMI_M_AHB_CLK>, 1518 <&mmcc HDMI_S_AHB_CLK>; 1519 clock-names = "core", 1520 "master_iface", 1521 "slave_iface"; 1522 1523 phys = <&hdmi_phy>; 1524 1525 status = "disabled"; 1526 1527 ports { 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 1531 port@0 { 1532 reg = <0>; 1533 hdmi_in: endpoint { 1534 }; 1535 }; 1536 1537 port@1 { 1538 reg = <1>; 1539 hdmi_out: endpoint { 1540 }; 1541 }; 1542 }; 1543 }; 1544 1545 hdmi_phy: phy@4a00400 { 1546 compatible = "qcom,hdmi-phy-8960"; 1547 reg = <0x4a00400 0x60>, 1548 <0x4a00500 0x100>; 1549 reg-names = "hdmi_phy", 1550 "hdmi_pll"; 1551 1552 clocks = <&mmcc HDMI_S_AHB_CLK>; 1553 clock-names = "slave_iface"; 1554 #phy-cells = <0>; 1555 #clock-cells = <0>; 1556 1557 status = "disabled"; 1558 }; 1559 1560 mdp: display-controller@5100000 { 1561 compatible = "qcom,mdp4"; 1562 reg = <0x05100000 0xf0000>; 1563 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1564 clocks = <&mmcc MDP_CLK>, 1565 <&mmcc MDP_AHB_CLK>, 1566 <&mmcc MDP_AXI_CLK>, 1567 <&mmcc MDP_LUT_CLK>, 1568 <&mmcc HDMI_TV_CLK>, 1569 <&mmcc MDP_TV_CLK>; 1570 clock-names = "core_clk", 1571 "iface_clk", 1572 "bus_clk", 1573 "lut_clk", 1574 "hdmi_clk", 1575 "tv_clk"; 1576 1577 iommus = <&mdp_port0 0 1578 &mdp_port0 2 1579 &mdp_port1 0 1580 &mdp_port1 2>; 1581 1582 ports { 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 1586 port@0 { 1587 reg = <0>; 1588 mdp_lvds_out: endpoint { 1589 }; 1590 }; 1591 1592 port@1 { 1593 reg = <1>; 1594 mdp_dsi1_out: endpoint { 1595 }; 1596 }; 1597 1598 port@2 { 1599 reg = <2>; 1600 mdp_dsi2_out: endpoint { 1601 }; 1602 }; 1603 1604 port@3 { 1605 reg = <3>; 1606 mdp_dtv_out: endpoint { 1607 }; 1608 }; 1609 }; 1610 }; 1611 1612 riva: riva-pil@3200800 { 1613 compatible = "qcom,riva-pil"; 1614 1615 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1616 reg-names = "ccu", "dxe", "pmu"; 1617 1618 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1619 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1620 interrupt-names = "wdog", "fatal"; 1621 1622 memory-region = <&wcnss_mem>; 1623 1624 vddcx-supply = <&pm8921_s3>; 1625 vddmx-supply = <&pm8921_l24>; 1626 vddpx-supply = <&pm8921_s4>; 1627 1628 status = "disabled"; 1629 1630 iris { 1631 compatible = "qcom,wcn3660"; 1632 1633 clocks = <&cxo_board>; 1634 clock-names = "xo"; 1635 1636 vddxo-supply = <&pm8921_l4>; 1637 vddrfa-supply = <&pm8921_s2>; 1638 vddpa-supply = <&pm8921_l10>; 1639 vdddig-supply = <&pm8921_lvs2>; 1640 }; 1641 1642 smd-edge { 1643 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1644 1645 qcom,ipc = <&l2cc 8 25>; 1646 qcom,smd-edge = <6>; 1647 1648 label = "riva"; 1649 1650 wcnss { 1651 compatible = "qcom,wcnss"; 1652 qcom,smd-channels = "WCNSS_CTRL"; 1653 1654 qcom,mmio = <&riva>; 1655 1656 bluetooth { 1657 compatible = "qcom,wcnss-bt"; 1658 }; 1659 1660 wifi { 1661 compatible = "qcom,wcnss-wlan"; 1662 1663 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1665 interrupt-names = "tx", "rx"; 1666 1667 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1668 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1669 }; 1670 }; 1671 }; 1672 }; 1673 1674 etb@1a01000 { 1675 compatible = "arm,coresight-etb10", "arm,primecell"; 1676 reg = <0x1a01000 0x1000>; 1677 1678 clocks = <&rpmcc RPM_QDSS_CLK>; 1679 clock-names = "apb_pclk"; 1680 1681 in-ports { 1682 port { 1683 etb_in: endpoint { 1684 remote-endpoint = <&replicator_out0>; 1685 }; 1686 }; 1687 }; 1688 }; 1689 1690 tpiu@1a03000 { 1691 compatible = "arm,coresight-tpiu", "arm,primecell"; 1692 reg = <0x1a03000 0x1000>; 1693 1694 clocks = <&rpmcc RPM_QDSS_CLK>; 1695 clock-names = "apb_pclk"; 1696 1697 in-ports { 1698 port { 1699 tpiu_in: endpoint { 1700 remote-endpoint = <&replicator_out1>; 1701 }; 1702 }; 1703 }; 1704 }; 1705 1706 replicator { 1707 compatible = "arm,coresight-static-replicator"; 1708 1709 clocks = <&rpmcc RPM_QDSS_CLK>; 1710 clock-names = "apb_pclk"; 1711 1712 out-ports { 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 1716 port@0 { 1717 reg = <0>; 1718 replicator_out0: endpoint { 1719 remote-endpoint = <&etb_in>; 1720 }; 1721 }; 1722 port@1 { 1723 reg = <1>; 1724 replicator_out1: endpoint { 1725 remote-endpoint = <&tpiu_in>; 1726 }; 1727 }; 1728 }; 1729 1730 in-ports { 1731 port { 1732 replicator_in: endpoint { 1733 remote-endpoint = <&funnel_out>; 1734 }; 1735 }; 1736 }; 1737 }; 1738 1739 funnel@1a04000 { 1740 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1741 reg = <0x1a04000 0x1000>; 1742 1743 clocks = <&rpmcc RPM_QDSS_CLK>; 1744 clock-names = "apb_pclk"; 1745 1746 in-ports { 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 1750 /* 1751 * Not described input ports: 1752 * 2 - connected to STM component 1753 * 3 - not-connected 1754 * 6 - not-connected 1755 * 7 - not-connected 1756 */ 1757 port@0 { 1758 reg = <0>; 1759 funnel_in0: endpoint { 1760 remote-endpoint = <&etm0_out>; 1761 }; 1762 }; 1763 port@1 { 1764 reg = <1>; 1765 funnel_in1: endpoint { 1766 remote-endpoint = <&etm1_out>; 1767 }; 1768 }; 1769 port@4 { 1770 reg = <4>; 1771 funnel_in4: endpoint { 1772 remote-endpoint = <&etm2_out>; 1773 }; 1774 }; 1775 port@5 { 1776 reg = <5>; 1777 funnel_in5: endpoint { 1778 remote-endpoint = <&etm3_out>; 1779 }; 1780 }; 1781 }; 1782 1783 out-ports { 1784 port { 1785 funnel_out: endpoint { 1786 remote-endpoint = <&replicator_in>; 1787 }; 1788 }; 1789 }; 1790 }; 1791 1792 etm@1a1c000 { 1793 compatible = "arm,coresight-etm3x", "arm,primecell"; 1794 reg = <0x1a1c000 0x1000>; 1795 1796 clocks = <&rpmcc RPM_QDSS_CLK>; 1797 clock-names = "apb_pclk"; 1798 1799 cpu = <&CPU0>; 1800 1801 out-ports { 1802 port { 1803 etm0_out: endpoint { 1804 remote-endpoint = <&funnel_in0>; 1805 }; 1806 }; 1807 }; 1808 }; 1809 1810 etm@1a1d000 { 1811 compatible = "arm,coresight-etm3x", "arm,primecell"; 1812 reg = <0x1a1d000 0x1000>; 1813 1814 clocks = <&rpmcc RPM_QDSS_CLK>; 1815 clock-names = "apb_pclk"; 1816 1817 cpu = <&CPU1>; 1818 1819 out-ports { 1820 port { 1821 etm1_out: endpoint { 1822 remote-endpoint = <&funnel_in1>; 1823 }; 1824 }; 1825 }; 1826 }; 1827 1828 etm@1a1e000 { 1829 compatible = "arm,coresight-etm3x", "arm,primecell"; 1830 reg = <0x1a1e000 0x1000>; 1831 1832 clocks = <&rpmcc RPM_QDSS_CLK>; 1833 clock-names = "apb_pclk"; 1834 1835 cpu = <&CPU2>; 1836 1837 out-ports { 1838 port { 1839 etm2_out: endpoint { 1840 remote-endpoint = <&funnel_in4>; 1841 }; 1842 }; 1843 }; 1844 }; 1845 1846 etm@1a1f000 { 1847 compatible = "arm,coresight-etm3x", "arm,primecell"; 1848 reg = <0x1a1f000 0x1000>; 1849 1850 clocks = <&rpmcc RPM_QDSS_CLK>; 1851 clock-names = "apb_pclk"; 1852 1853 cpu = <&CPU3>; 1854 1855 out-ports { 1856 port { 1857 etm3_out: endpoint { 1858 remote-endpoint = <&funnel_in5>; 1859 }; 1860 }; 1861 }; 1862 }; 1863 }; 1864}; 1865#include "qcom-apq8064-pins.dtsi" 1866