1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 cpsw0_phy_gmii_sel: phy@4044 { 43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; 44 ti,qsgmii-main-ports = <1>; 45 reg = <0x4044 0x10>; 46 #phy-cells = <1>; 47 }; 48 49 usb_serdes_mux: mux-controller@4000 { 50 compatible = "mmio-mux"; 51 #mux-control-cells = <1>; 52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 53 }; 54 }; 55 56 gic500: interrupt-controller@1800000 { 57 compatible = "arm,gic-v3"; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 #interrupt-cells = <3>; 62 interrupt-controller; 63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 64 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 65 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 66 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 67 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 68 69 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 72 gic_its: msi-controller@1820000 { 73 compatible = "arm,gic-v3-its"; 74 reg = <0x00 0x01820000 0x00 0x10000>; 75 socionext,synquacer-pre-its = <0x1000000 0x400000>; 76 msi-controller; 77 #msi-cells = <1>; 78 }; 79 }; 80 81 main_gpio_intr: interrupt-controller@a00000 { 82 compatible = "ti,sci-intr"; 83 reg = <0x00 0x00a00000 0x00 0x800>; 84 ti,intr-trigger-type = <1>; 85 interrupt-controller; 86 interrupt-parent = <&gic500>; 87 #interrupt-cells = <1>; 88 ti,sci = <&dmsc>; 89 ti,sci-dev-id = <131>; 90 ti,interrupt-ranges = <8 392 56>; 91 }; 92 93 main_navss: bus@30000000 { 94 compatible = "simple-mfd"; 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 98 ti,sci-dev-id = <199>; 99 dma-coherent; 100 dma-ranges; 101 102 main_navss_intr: interrupt-controller@310e0000 { 103 compatible = "ti,sci-intr"; 104 reg = <0x00 0x310e0000 0x00 0x4000>; 105 ti,intr-trigger-type = <4>; 106 interrupt-controller; 107 interrupt-parent = <&gic500>; 108 #interrupt-cells = <1>; 109 ti,sci = <&dmsc>; 110 ti,sci-dev-id = <213>; 111 ti,interrupt-ranges = <0 64 64>, 112 <64 448 64>, 113 <128 672 64>; 114 }; 115 116 main_udmass_inta: msi-controller@33d00000 { 117 compatible = "ti,sci-inta"; 118 reg = <0x00 0x33d00000 0x00 0x100000>; 119 interrupt-controller; 120 #interrupt-cells = <0>; 121 interrupt-parent = <&main_navss_intr>; 122 msi-controller; 123 ti,sci = <&dmsc>; 124 ti,sci-dev-id = <209>; 125 ti,interrupt-ranges = <0 0 256>; 126 }; 127 128 secure_proxy_main: mailbox@32c00000 { 129 compatible = "ti,am654-secure-proxy"; 130 #mbox-cells = <1>; 131 reg-names = "target_data", "rt", "scfg"; 132 reg = <0x00 0x32c00000 0x00 0x100000>, 133 <0x00 0x32400000 0x00 0x100000>, 134 <0x00 0x32800000 0x00 0x100000>; 135 interrupt-names = "rx_011"; 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 137 }; 138 139 hwspinlock: spinlock@30e00000 { 140 compatible = "ti,am654-hwspinlock"; 141 reg = <0x00 0x30e00000 0x00 0x1000>; 142 #hwlock-cells = <1>; 143 }; 144 145 mailbox0_cluster0: mailbox@31f80000 { 146 compatible = "ti,am654-mailbox"; 147 reg = <0x00 0x31f80000 0x00 0x200>; 148 #mbox-cells = <1>; 149 ti,mbox-num-users = <4>; 150 ti,mbox-num-fifos = <16>; 151 interrupt-parent = <&main_navss_intr>; 152 status = "disabled"; 153 }; 154 155 mailbox0_cluster1: mailbox@31f81000 { 156 compatible = "ti,am654-mailbox"; 157 reg = <0x00 0x31f81000 0x00 0x200>; 158 #mbox-cells = <1>; 159 ti,mbox-num-users = <4>; 160 ti,mbox-num-fifos = <16>; 161 interrupt-parent = <&main_navss_intr>; 162 status = "disabled"; 163 }; 164 165 mailbox0_cluster2: mailbox@31f82000 { 166 compatible = "ti,am654-mailbox"; 167 reg = <0x00 0x31f82000 0x00 0x200>; 168 #mbox-cells = <1>; 169 ti,mbox-num-users = <4>; 170 ti,mbox-num-fifos = <16>; 171 interrupt-parent = <&main_navss_intr>; 172 status = "disabled"; 173 }; 174 175 mailbox0_cluster3: mailbox@31f83000 { 176 compatible = "ti,am654-mailbox"; 177 reg = <0x00 0x31f83000 0x00 0x200>; 178 #mbox-cells = <1>; 179 ti,mbox-num-users = <4>; 180 ti,mbox-num-fifos = <16>; 181 interrupt-parent = <&main_navss_intr>; 182 status = "disabled"; 183 }; 184 185 mailbox0_cluster4: mailbox@31f84000 { 186 compatible = "ti,am654-mailbox"; 187 reg = <0x00 0x31f84000 0x00 0x200>; 188 #mbox-cells = <1>; 189 ti,mbox-num-users = <4>; 190 ti,mbox-num-fifos = <16>; 191 interrupt-parent = <&main_navss_intr>; 192 status = "disabled"; 193 }; 194 195 mailbox0_cluster5: mailbox@31f85000 { 196 compatible = "ti,am654-mailbox"; 197 reg = <0x00 0x31f85000 0x00 0x200>; 198 #mbox-cells = <1>; 199 ti,mbox-num-users = <4>; 200 ti,mbox-num-fifos = <16>; 201 interrupt-parent = <&main_navss_intr>; 202 status = "disabled"; 203 }; 204 205 mailbox0_cluster6: mailbox@31f86000 { 206 compatible = "ti,am654-mailbox"; 207 reg = <0x00 0x31f86000 0x00 0x200>; 208 #mbox-cells = <1>; 209 ti,mbox-num-users = <4>; 210 ti,mbox-num-fifos = <16>; 211 interrupt-parent = <&main_navss_intr>; 212 status = "disabled"; 213 }; 214 215 mailbox0_cluster7: mailbox@31f87000 { 216 compatible = "ti,am654-mailbox"; 217 reg = <0x00 0x31f87000 0x00 0x200>; 218 #mbox-cells = <1>; 219 ti,mbox-num-users = <4>; 220 ti,mbox-num-fifos = <16>; 221 interrupt-parent = <&main_navss_intr>; 222 status = "disabled"; 223 }; 224 225 mailbox0_cluster8: mailbox@31f88000 { 226 compatible = "ti,am654-mailbox"; 227 reg = <0x00 0x31f88000 0x00 0x200>; 228 #mbox-cells = <1>; 229 ti,mbox-num-users = <4>; 230 ti,mbox-num-fifos = <16>; 231 interrupt-parent = <&main_navss_intr>; 232 status = "disabled"; 233 }; 234 235 mailbox0_cluster9: mailbox@31f89000 { 236 compatible = "ti,am654-mailbox"; 237 reg = <0x00 0x31f89000 0x00 0x200>; 238 #mbox-cells = <1>; 239 ti,mbox-num-users = <4>; 240 ti,mbox-num-fifos = <16>; 241 interrupt-parent = <&main_navss_intr>; 242 status = "disabled"; 243 }; 244 245 mailbox0_cluster10: mailbox@31f8a000 { 246 compatible = "ti,am654-mailbox"; 247 reg = <0x00 0x31f8a000 0x00 0x200>; 248 #mbox-cells = <1>; 249 ti,mbox-num-users = <4>; 250 ti,mbox-num-fifos = <16>; 251 interrupt-parent = <&main_navss_intr>; 252 status = "disabled"; 253 }; 254 255 mailbox0_cluster11: mailbox@31f8b000 { 256 compatible = "ti,am654-mailbox"; 257 reg = <0x00 0x31f8b000 0x00 0x200>; 258 #mbox-cells = <1>; 259 ti,mbox-num-users = <4>; 260 ti,mbox-num-fifos = <16>; 261 interrupt-parent = <&main_navss_intr>; 262 status = "disabled"; 263 }; 264 265 main_ringacc: ringacc@3c000000 { 266 compatible = "ti,am654-navss-ringacc"; 267 reg = <0x00 0x3c000000 0x00 0x400000>, 268 <0x00 0x38000000 0x00 0x400000>, 269 <0x00 0x31120000 0x00 0x100>, 270 <0x00 0x33000000 0x00 0x40000>, 271 <0x00 0x31080000 0x00 0x40000>; 272 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 273 ti,num-rings = <1024>; 274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 275 ti,sci = <&dmsc>; 276 ti,sci-dev-id = <211>; 277 msi-parent = <&main_udmass_inta>; 278 }; 279 280 main_udmap: dma-controller@31150000 { 281 compatible = "ti,j721e-navss-main-udmap"; 282 reg = <0x00 0x31150000 0x00 0x100>, 283 <0x00 0x34000000 0x00 0x100000>, 284 <0x00 0x35000000 0x00 0x100000>; 285 reg-names = "gcfg", "rchanrt", "tchanrt"; 286 msi-parent = <&main_udmass_inta>; 287 #dma-cells = <1>; 288 289 ti,sci = <&dmsc>; 290 ti,sci-dev-id = <212>; 291 ti,ringacc = <&main_ringacc>; 292 293 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 294 <0x0f>, /* TX_HCHAN */ 295 <0x10>; /* TX_UHCHAN */ 296 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 297 <0x0b>, /* RX_HCHAN */ 298 <0x0c>; /* RX_UHCHAN */ 299 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 300 }; 301 302 cpts@310d0000 { 303 compatible = "ti,j721e-cpts"; 304 reg = <0x00 0x310d0000 0x00 0x400>; 305 reg-names = "cpts"; 306 clocks = <&k3_clks 201 1>; 307 clock-names = "cpts"; 308 interrupts-extended = <&main_navss_intr 391>; 309 interrupt-names = "cpts"; 310 ti,cpts-periodic-outputs = <6>; 311 ti,cpts-ext-ts-inputs = <8>; 312 }; 313 }; 314 315 cpsw0: ethernet@c000000 { 316 compatible = "ti,j7200-cpswxg-nuss"; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 reg = <0x00 0xc000000 0x00 0x200000>; 320 reg-names = "cpsw_nuss"; 321 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 322 clocks = <&k3_clks 19 33>; 323 clock-names = "fck"; 324 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 325 326 dmas = <&main_udmap 0xca00>, 327 <&main_udmap 0xca01>, 328 <&main_udmap 0xca02>, 329 <&main_udmap 0xca03>, 330 <&main_udmap 0xca04>, 331 <&main_udmap 0xca05>, 332 <&main_udmap 0xca06>, 333 <&main_udmap 0xca07>, 334 <&main_udmap 0x4a00>; 335 dma-names = "tx0", "tx1", "tx2", "tx3", 336 "tx4", "tx5", "tx6", "tx7", 337 "rx"; 338 339 status = "disabled"; 340 341 ethernet-ports { 342 #address-cells = <1>; 343 #size-cells = <0>; 344 cpsw0_port1: port@1 { 345 reg = <1>; 346 ti,mac-only; 347 label = "port1"; 348 status = "disabled"; 349 }; 350 351 cpsw0_port2: port@2 { 352 reg = <2>; 353 ti,mac-only; 354 label = "port2"; 355 status = "disabled"; 356 }; 357 358 cpsw0_port3: port@3 { 359 reg = <3>; 360 ti,mac-only; 361 label = "port3"; 362 status = "disabled"; 363 }; 364 365 cpsw0_port4: port@4 { 366 reg = <4>; 367 ti,mac-only; 368 label = "port4"; 369 status = "disabled"; 370 }; 371 }; 372 373 cpsw5g_mdio: mdio@f00 { 374 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 375 reg = <0x00 0xf00 0x00 0x100>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&k3_clks 19 33>; 379 clock-names = "fck"; 380 bus_freq = <1000000>; 381 status = "disabled"; 382 }; 383 384 cpts@3d000 { 385 compatible = "ti,j721e-cpts"; 386 reg = <0x00 0x3d000 0x00 0x400>; 387 clocks = <&k3_clks 19 16>; 388 clock-names = "cpts"; 389 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 390 interrupt-names = "cpts"; 391 ti,cpts-ext-ts-inputs = <4>; 392 ti,cpts-periodic-outputs = <2>; 393 }; 394 }; 395 396 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 397 main_timerio_input: pinctrl@104200 { 398 compatible = "ti,j7200-padconf", "pinctrl-single"; 399 reg = <0x0 0x104200 0x0 0x50>; 400 #pinctrl-cells = <1>; 401 pinctrl-single,register-width = <32>; 402 pinctrl-single,function-mask = <0x000001ff>; 403 }; 404 405 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 406 main_timerio_output: pinctrl@104280 { 407 compatible = "ti,j7200-padconf", "pinctrl-single"; 408 reg = <0x0 0x104280 0x0 0x20>; 409 #pinctrl-cells = <1>; 410 pinctrl-single,register-width = <32>; 411 pinctrl-single,function-mask = <0x0000001f>; 412 }; 413 414 main_pmx0: pinctrl@11c000 { 415 compatible = "ti,j7200-padconf", "pinctrl-single"; 416 /* Proxy 0 addressing */ 417 reg = <0x00 0x11c000 0x00 0x10c>; 418 #pinctrl-cells = <1>; 419 pinctrl-single,register-width = <32>; 420 pinctrl-single,function-mask = <0xffffffff>; 421 }; 422 423 main_pmx1: pinctrl@11c110 { 424 compatible = "ti,j7200-padconf", "pinctrl-single"; 425 /* Proxy 0 addressing */ 426 reg = <0x00 0x11c110 0x00 0x004>; 427 #pinctrl-cells = <1>; 428 pinctrl-single,register-width = <32>; 429 pinctrl-single,function-mask = <0xffffffff>; 430 }; 431 432 main_pmx2: pinctrl@11c11c { 433 compatible = "ti,j7200-padconf", "pinctrl-single"; 434 /* Proxy 0 addressing */ 435 reg = <0x00 0x11c11c 0x00 0x00c>; 436 #pinctrl-cells = <1>; 437 pinctrl-single,register-width = <32>; 438 pinctrl-single,function-mask = <0xffffffff>; 439 }; 440 441 main_pmx3: pinctrl@11c164 { 442 compatible = "ti,j7200-padconf", "pinctrl-single"; 443 /* Proxy 0 addressing */ 444 reg = <0x00 0x11c164 0x00 0x008>; 445 #pinctrl-cells = <1>; 446 pinctrl-single,register-width = <32>; 447 pinctrl-single,function-mask = <0xffffffff>; 448 }; 449 450 main_uart0: serial@2800000 { 451 compatible = "ti,j721e-uart", "ti,am654-uart"; 452 reg = <0x00 0x02800000 0x00 0x100>; 453 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 454 clock-frequency = <48000000>; 455 current-speed = <115200>; 456 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 457 clocks = <&k3_clks 146 2>; 458 clock-names = "fclk"; 459 status = "disabled"; 460 }; 461 462 main_uart1: serial@2810000 { 463 compatible = "ti,j721e-uart", "ti,am654-uart"; 464 reg = <0x00 0x02810000 0x00 0x100>; 465 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 466 clock-frequency = <48000000>; 467 current-speed = <115200>; 468 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 469 clocks = <&k3_clks 278 2>; 470 clock-names = "fclk"; 471 status = "disabled"; 472 }; 473 474 main_uart2: serial@2820000 { 475 compatible = "ti,j721e-uart", "ti,am654-uart"; 476 reg = <0x00 0x02820000 0x00 0x100>; 477 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 478 clock-frequency = <48000000>; 479 current-speed = <115200>; 480 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 481 clocks = <&k3_clks 279 2>; 482 clock-names = "fclk"; 483 status = "disabled"; 484 }; 485 486 main_uart3: serial@2830000 { 487 compatible = "ti,j721e-uart", "ti,am654-uart"; 488 reg = <0x00 0x02830000 0x00 0x100>; 489 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 490 clock-frequency = <48000000>; 491 current-speed = <115200>; 492 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 493 clocks = <&k3_clks 280 2>; 494 clock-names = "fclk"; 495 status = "disabled"; 496 }; 497 498 main_uart4: serial@2840000 { 499 compatible = "ti,j721e-uart", "ti,am654-uart"; 500 reg = <0x00 0x02840000 0x00 0x100>; 501 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 502 clock-frequency = <48000000>; 503 current-speed = <115200>; 504 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 505 clocks = <&k3_clks 281 2>; 506 clock-names = "fclk"; 507 status = "disabled"; 508 }; 509 510 main_uart5: serial@2850000 { 511 compatible = "ti,j721e-uart", "ti,am654-uart"; 512 reg = <0x00 0x02850000 0x00 0x100>; 513 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 514 clock-frequency = <48000000>; 515 current-speed = <115200>; 516 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 517 clocks = <&k3_clks 282 2>; 518 clock-names = "fclk"; 519 status = "disabled"; 520 }; 521 522 main_uart6: serial@2860000 { 523 compatible = "ti,j721e-uart", "ti,am654-uart"; 524 reg = <0x00 0x02860000 0x00 0x100>; 525 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 526 clock-frequency = <48000000>; 527 current-speed = <115200>; 528 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 529 clocks = <&k3_clks 283 2>; 530 clock-names = "fclk"; 531 status = "disabled"; 532 }; 533 534 main_uart7: serial@2870000 { 535 compatible = "ti,j721e-uart", "ti,am654-uart"; 536 reg = <0x00 0x02870000 0x00 0x100>; 537 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 538 clock-frequency = <48000000>; 539 current-speed = <115200>; 540 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 541 clocks = <&k3_clks 284 2>; 542 clock-names = "fclk"; 543 status = "disabled"; 544 }; 545 546 main_uart8: serial@2880000 { 547 compatible = "ti,j721e-uart", "ti,am654-uart"; 548 reg = <0x00 0x02880000 0x00 0x100>; 549 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 550 clock-frequency = <48000000>; 551 current-speed = <115200>; 552 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 553 clocks = <&k3_clks 285 2>; 554 clock-names = "fclk"; 555 status = "disabled"; 556 }; 557 558 main_uart9: serial@2890000 { 559 compatible = "ti,j721e-uart", "ti,am654-uart"; 560 reg = <0x00 0x02890000 0x00 0x100>; 561 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 562 clock-frequency = <48000000>; 563 current-speed = <115200>; 564 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 565 clocks = <&k3_clks 286 2>; 566 clock-names = "fclk"; 567 status = "disabled"; 568 }; 569 570 main_i2c0: i2c@2000000 { 571 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 572 reg = <0x00 0x2000000 0x00 0x100>; 573 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 clock-names = "fck"; 577 clocks = <&k3_clks 187 1>; 578 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 579 status = "disabled"; 580 }; 581 582 main_i2c1: i2c@2010000 { 583 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 584 reg = <0x00 0x2010000 0x00 0x100>; 585 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 clock-names = "fck"; 589 clocks = <&k3_clks 188 1>; 590 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 591 status = "disabled"; 592 }; 593 594 main_i2c2: i2c@2020000 { 595 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 596 reg = <0x00 0x2020000 0x00 0x100>; 597 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 clock-names = "fck"; 601 clocks = <&k3_clks 189 1>; 602 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 603 status = "disabled"; 604 }; 605 606 main_i2c3: i2c@2030000 { 607 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 608 reg = <0x00 0x2030000 0x00 0x100>; 609 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 clock-names = "fck"; 613 clocks = <&k3_clks 190 1>; 614 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 615 status = "disabled"; 616 }; 617 618 main_i2c4: i2c@2040000 { 619 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 620 reg = <0x00 0x2040000 0x00 0x100>; 621 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 clock-names = "fck"; 625 clocks = <&k3_clks 191 1>; 626 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 627 status = "disabled"; 628 }; 629 630 main_i2c5: i2c@2050000 { 631 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 632 reg = <0x00 0x2050000 0x00 0x100>; 633 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 clock-names = "fck"; 637 clocks = <&k3_clks 192 1>; 638 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 639 status = "disabled"; 640 }; 641 642 main_i2c6: i2c@2060000 { 643 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 644 reg = <0x00 0x2060000 0x00 0x100>; 645 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 clock-names = "fck"; 649 clocks = <&k3_clks 193 1>; 650 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 651 status = "disabled"; 652 }; 653 654 main_sdhci0: mmc@4f80000 { 655 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 656 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 657 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 658 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 659 clock-names = "clk_ahb", "clk_xin"; 660 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 661 ti,otap-del-sel-legacy = <0x0>; 662 ti,otap-del-sel-mmc-hs = <0x0>; 663 ti,otap-del-sel-ddr52 = <0x6>; 664 ti,otap-del-sel-hs200 = <0x8>; 665 ti,otap-del-sel-hs400 = <0x5>; 666 ti,itap-del-sel-legacy = <0x10>; 667 ti,itap-del-sel-mmc-hs = <0xa>; 668 ti,strobe-sel = <0x77>; 669 ti,clkbuf-sel = <0x7>; 670 ti,trm-icp = <0x8>; 671 bus-width = <8>; 672 mmc-ddr-1_8v; 673 mmc-hs200-1_8v; 674 mmc-hs400-1_8v; 675 dma-coherent; 676 status = "disabled"; 677 }; 678 679 main_sdhci1: mmc@4fb0000 { 680 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 681 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 682 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 683 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 684 clock-names = "clk_ahb", "clk_xin"; 685 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 686 ti,otap-del-sel-legacy = <0x0>; 687 ti,otap-del-sel-sd-hs = <0x0>; 688 ti,otap-del-sel-sdr12 = <0xf>; 689 ti,otap-del-sel-sdr25 = <0xf>; 690 ti,otap-del-sel-sdr50 = <0xc>; 691 ti,otap-del-sel-sdr104 = <0x5>; 692 ti,otap-del-sel-ddr50 = <0xc>; 693 ti,itap-del-sel-legacy = <0x0>; 694 ti,itap-del-sel-sd-hs = <0x0>; 695 ti,itap-del-sel-sdr12 = <0x0>; 696 ti,itap-del-sel-sdr25 = <0x0>; 697 ti,clkbuf-sel = <0x7>; 698 ti,trm-icp = <0x8>; 699 dma-coherent; 700 status = "disabled"; 701 }; 702 703 serdes_wiz0: wiz@5060000 { 704 compatible = "ti,j721e-wiz-10g"; 705 #address-cells = <1>; 706 #size-cells = <1>; 707 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 708 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 709 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 710 num-lanes = <4>; 711 #reset-cells = <1>; 712 ranges = <0x5060000 0x0 0x5060000 0x10000>; 713 714 assigned-clocks = <&k3_clks 292 85>; 715 assigned-clock-parents = <&k3_clks 292 89>; 716 717 wiz0_pll0_refclk: pll0-refclk { 718 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 719 clock-output-names = "wiz0_pll0_refclk"; 720 #clock-cells = <0>; 721 assigned-clocks = <&wiz0_pll0_refclk>; 722 assigned-clock-parents = <&k3_clks 292 85>; 723 }; 724 725 wiz0_pll1_refclk: pll1-refclk { 726 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 727 clock-output-names = "wiz0_pll1_refclk"; 728 #clock-cells = <0>; 729 assigned-clocks = <&wiz0_pll1_refclk>; 730 assigned-clock-parents = <&k3_clks 292 85>; 731 }; 732 733 wiz0_refclk_dig: refclk-dig { 734 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 735 clock-output-names = "wiz0_refclk_dig"; 736 #clock-cells = <0>; 737 assigned-clocks = <&wiz0_refclk_dig>; 738 assigned-clock-parents = <&k3_clks 292 85>; 739 }; 740 741 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 742 clocks = <&wiz0_refclk_dig>; 743 #clock-cells = <0>; 744 }; 745 746 serdes0: serdes@5060000 { 747 compatible = "ti,j721e-serdes-10g"; 748 reg = <0x05060000 0x00010000>; 749 reg-names = "torrent_phy"; 750 resets = <&serdes_wiz0 0>; 751 reset-names = "torrent_reset"; 752 clocks = <&wiz0_pll0_refclk>; 753 clock-names = "refclk"; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 }; 757 }; 758 759 pcie1_rc: pcie@2910000 { 760 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 761 reg = <0x00 0x02910000 0x00 0x1000>, 762 <0x00 0x02917000 0x00 0x400>, 763 <0x00 0x0d800000 0x00 0x00800000>, 764 <0x00 0x18000000 0x00 0x00001000>; 765 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 766 interrupt-names = "link_state"; 767 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 768 device_type = "pci"; 769 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 770 max-link-speed = <3>; 771 num-lanes = <4>; 772 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 773 clocks = <&k3_clks 240 6>; 774 clock-names = "fck"; 775 #address-cells = <3>; 776 #size-cells = <2>; 777 bus-range = <0x0 0xff>; 778 cdns,no-bar-match-nbits = <64>; 779 vendor-id = <0x104c>; 780 device-id = <0xb00f>; 781 msi-map = <0x0 &gic_its 0x0 0x10000>; 782 dma-coherent; 783 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 784 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 785 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 786 }; 787 788 pcie1_ep: pcie-ep@2910000 { 789 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 790 reg = <0x00 0x02910000 0x00 0x1000>, 791 <0x00 0x02917000 0x00 0x400>, 792 <0x00 0x0d800000 0x00 0x00800000>, 793 <0x00 0x18000000 0x00 0x08000000>; 794 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 795 interrupt-names = "link_state"; 796 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 797 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 798 max-link-speed = <3>; 799 num-lanes = <4>; 800 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 801 clocks = <&k3_clks 240 6>; 802 clock-names = "fck"; 803 max-functions = /bits/ 8 <6>; 804 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 805 dma-coherent; 806 }; 807 808 usbss0: cdns-usb@4104000 { 809 compatible = "ti,j721e-usb"; 810 reg = <0x00 0x4104000 0x00 0x100>; 811 dma-coherent; 812 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 813 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 814 clock-names = "ref", "lpm"; 815 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 816 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 817 #address-cells = <2>; 818 #size-cells = <2>; 819 ranges; 820 821 usb0: usb@6000000 { 822 compatible = "cdns,usb3"; 823 reg = <0x00 0x6000000 0x00 0x10000>, 824 <0x00 0x6010000 0x00 0x10000>, 825 <0x00 0x6020000 0x00 0x10000>; 826 reg-names = "otg", "xhci", "dev"; 827 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 828 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 829 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 830 interrupt-names = "host", 831 "peripheral", 832 "otg"; 833 maximum-speed = "super-speed"; 834 dr_mode = "otg"; 835 cdns,phyrst-a-enable; 836 }; 837 }; 838 839 main_gpio0: gpio@600000 { 840 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 841 reg = <0x00 0x00600000 0x00 0x100>; 842 gpio-controller; 843 #gpio-cells = <2>; 844 interrupt-parent = <&main_gpio_intr>; 845 interrupts = <145>, <146>, <147>, <148>, 846 <149>; 847 interrupt-controller; 848 #interrupt-cells = <2>; 849 ti,ngpio = <69>; 850 ti,davinci-gpio-unbanked = <0>; 851 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 852 clocks = <&k3_clks 105 0>; 853 clock-names = "gpio"; 854 status = "disabled"; 855 }; 856 857 main_gpio2: gpio@610000 { 858 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 859 reg = <0x00 0x00610000 0x00 0x100>; 860 gpio-controller; 861 #gpio-cells = <2>; 862 interrupt-parent = <&main_gpio_intr>; 863 interrupts = <154>, <155>, <156>, <157>, 864 <158>; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 ti,ngpio = <69>; 868 ti,davinci-gpio-unbanked = <0>; 869 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 870 clocks = <&k3_clks 107 0>; 871 clock-names = "gpio"; 872 status = "disabled"; 873 }; 874 875 main_gpio4: gpio@620000 { 876 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 877 reg = <0x00 0x00620000 0x00 0x100>; 878 gpio-controller; 879 #gpio-cells = <2>; 880 interrupt-parent = <&main_gpio_intr>; 881 interrupts = <163>, <164>, <165>, <166>, 882 <167>; 883 interrupt-controller; 884 #interrupt-cells = <2>; 885 ti,ngpio = <69>; 886 ti,davinci-gpio-unbanked = <0>; 887 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 888 clocks = <&k3_clks 109 0>; 889 clock-names = "gpio"; 890 status = "disabled"; 891 }; 892 893 main_gpio6: gpio@630000 { 894 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 895 reg = <0x00 0x00630000 0x00 0x100>; 896 gpio-controller; 897 #gpio-cells = <2>; 898 interrupt-parent = <&main_gpio_intr>; 899 interrupts = <172>, <173>, <174>, <175>, 900 <176>; 901 interrupt-controller; 902 #interrupt-cells = <2>; 903 ti,ngpio = <69>; 904 ti,davinci-gpio-unbanked = <0>; 905 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 906 clocks = <&k3_clks 111 0>; 907 clock-names = "gpio"; 908 status = "disabled"; 909 }; 910 911 main_spi0: spi@2100000 { 912 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 913 reg = <0x00 0x02100000 0x00 0x400>; 914 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 918 clocks = <&k3_clks 266 4>; 919 status = "disabled"; 920 }; 921 922 main_spi1: spi@2110000 { 923 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 924 reg = <0x00 0x02110000 0x00 0x400>; 925 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 929 clocks = <&k3_clks 267 4>; 930 status = "disabled"; 931 }; 932 933 main_spi2: spi@2120000 { 934 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 935 reg = <0x00 0x02120000 0x00 0x400>; 936 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 940 clocks = <&k3_clks 268 4>; 941 status = "disabled"; 942 }; 943 944 main_spi3: spi@2130000 { 945 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 946 reg = <0x00 0x02130000 0x00 0x400>; 947 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 951 clocks = <&k3_clks 269 4>; 952 status = "disabled"; 953 }; 954 955 main_spi4: spi@2140000 { 956 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 957 reg = <0x00 0x02140000 0x00 0x400>; 958 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 962 clocks = <&k3_clks 270 2>; 963 status = "disabled"; 964 }; 965 966 main_spi5: spi@2150000 { 967 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 968 reg = <0x00 0x02150000 0x00 0x400>; 969 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 973 clocks = <&k3_clks 271 4>; 974 status = "disabled"; 975 }; 976 977 main_spi6: spi@2160000 { 978 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 979 reg = <0x00 0x02160000 0x00 0x400>; 980 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 984 clocks = <&k3_clks 272 4>; 985 status = "disabled"; 986 }; 987 988 main_spi7: spi@2170000 { 989 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 990 reg = <0x00 0x02170000 0x00 0x400>; 991 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 995 clocks = <&k3_clks 273 4>; 996 status = "disabled"; 997 }; 998 999 watchdog0: watchdog@2200000 { 1000 compatible = "ti,j7-rti-wdt"; 1001 reg = <0x0 0x2200000 0x0 0x100>; 1002 clocks = <&k3_clks 252 1>; 1003 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1004 assigned-clocks = <&k3_clks 252 1>; 1005 assigned-clock-parents = <&k3_clks 252 5>; 1006 }; 1007 1008 watchdog1: watchdog@2210000 { 1009 compatible = "ti,j7-rti-wdt"; 1010 reg = <0x0 0x2210000 0x0 0x100>; 1011 clocks = <&k3_clks 253 1>; 1012 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1013 assigned-clocks = <&k3_clks 253 1>; 1014 assigned-clock-parents = <&k3_clks 253 5>; 1015 }; 1016 1017 main_timer0: timer@2400000 { 1018 compatible = "ti,am654-timer"; 1019 reg = <0x00 0x2400000 0x00 0x400>; 1020 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&k3_clks 49 1>; 1022 clock-names = "fck"; 1023 assigned-clocks = <&k3_clks 49 1>; 1024 assigned-clock-parents = <&k3_clks 49 2>; 1025 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1026 ti,timer-pwm; 1027 }; 1028 1029 main_timer1: timer@2410000 { 1030 compatible = "ti,am654-timer"; 1031 reg = <0x00 0x2410000 0x00 0x400>; 1032 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&k3_clks 50 1>; 1034 clock-names = "fck"; 1035 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; 1036 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; 1037 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1038 ti,timer-pwm; 1039 }; 1040 1041 main_timer2: timer@2420000 { 1042 compatible = "ti,am654-timer"; 1043 reg = <0x00 0x2420000 0x00 0x400>; 1044 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&k3_clks 51 1>; 1046 clock-names = "fck"; 1047 assigned-clocks = <&k3_clks 51 1>; 1048 assigned-clock-parents = <&k3_clks 51 2>; 1049 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1050 ti,timer-pwm; 1051 }; 1052 1053 main_timer3: timer@2430000 { 1054 compatible = "ti,am654-timer"; 1055 reg = <0x00 0x2430000 0x00 0x400>; 1056 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1057 clocks = <&k3_clks 52 1>; 1058 clock-names = "fck"; 1059 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; 1060 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; 1061 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1062 ti,timer-pwm; 1063 }; 1064 1065 main_timer4: timer@2440000 { 1066 compatible = "ti,am654-timer"; 1067 reg = <0x00 0x2440000 0x00 0x400>; 1068 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&k3_clks 53 1>; 1070 clock-names = "fck"; 1071 assigned-clocks = <&k3_clks 53 1>; 1072 assigned-clock-parents = <&k3_clks 53 2>; 1073 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1074 ti,timer-pwm; 1075 }; 1076 1077 main_timer5: timer@2450000 { 1078 compatible = "ti,am654-timer"; 1079 reg = <0x00 0x2450000 0x00 0x400>; 1080 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&k3_clks 54 1>; 1082 clock-names = "fck"; 1083 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; 1084 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; 1085 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1086 ti,timer-pwm; 1087 }; 1088 1089 main_timer6: timer@2460000 { 1090 compatible = "ti,am654-timer"; 1091 reg = <0x00 0x2460000 0x00 0x400>; 1092 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&k3_clks 55 1>; 1094 clock-names = "fck"; 1095 assigned-clocks = <&k3_clks 55 1>; 1096 assigned-clock-parents = <&k3_clks 55 2>; 1097 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1098 ti,timer-pwm; 1099 }; 1100 1101 main_timer7: timer@2470000 { 1102 compatible = "ti,am654-timer"; 1103 reg = <0x00 0x2470000 0x00 0x400>; 1104 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&k3_clks 57 1>; 1106 clock-names = "fck"; 1107 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; 1108 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; 1109 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1110 ti,timer-pwm; 1111 }; 1112 1113 main_timer8: timer@2480000 { 1114 compatible = "ti,am654-timer"; 1115 reg = <0x00 0x2480000 0x00 0x400>; 1116 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&k3_clks 58 1>; 1118 clock-names = "fck"; 1119 assigned-clocks = <&k3_clks 58 1>; 1120 assigned-clock-parents = <&k3_clks 58 2>; 1121 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1122 ti,timer-pwm; 1123 }; 1124 1125 main_timer9: timer@2490000 { 1126 compatible = "ti,am654-timer"; 1127 reg = <0x00 0x2490000 0x00 0x400>; 1128 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&k3_clks 59 1>; 1130 clock-names = "fck"; 1131 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; 1132 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; 1133 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1134 ti,timer-pwm; 1135 }; 1136 1137 main_timer10: timer@24a0000 { 1138 compatible = "ti,am654-timer"; 1139 reg = <0x00 0x24a0000 0x00 0x400>; 1140 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&k3_clks 60 1>; 1142 clock-names = "fck"; 1143 assigned-clocks = <&k3_clks 60 1>; 1144 assigned-clock-parents = <&k3_clks 60 2>; 1145 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1146 ti,timer-pwm; 1147 }; 1148 1149 main_timer11: timer@24b0000 { 1150 compatible = "ti,am654-timer"; 1151 reg = <0x00 0x24b0000 0x00 0x400>; 1152 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&k3_clks 62 1>; 1154 clock-names = "fck"; 1155 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; 1156 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; 1157 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1158 ti,timer-pwm; 1159 }; 1160 1161 main_timer12: timer@24c0000 { 1162 compatible = "ti,am654-timer"; 1163 reg = <0x00 0x24c0000 0x00 0x400>; 1164 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&k3_clks 63 1>; 1166 clock-names = "fck"; 1167 assigned-clocks = <&k3_clks 63 1>; 1168 assigned-clock-parents = <&k3_clks 63 2>; 1169 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1170 ti,timer-pwm; 1171 }; 1172 1173 main_timer13: timer@24d0000 { 1174 compatible = "ti,am654-timer"; 1175 reg = <0x00 0x24d0000 0x00 0x400>; 1176 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&k3_clks 64 1>; 1178 clock-names = "fck"; 1179 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; 1180 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; 1181 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1182 ti,timer-pwm; 1183 }; 1184 1185 main_timer14: timer@24e0000 { 1186 compatible = "ti,am654-timer"; 1187 reg = <0x00 0x24e0000 0x00 0x400>; 1188 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&k3_clks 65 1>; 1190 clock-names = "fck"; 1191 assigned-clocks = <&k3_clks 65 1>; 1192 assigned-clock-parents = <&k3_clks 65 2>; 1193 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1194 ti,timer-pwm; 1195 }; 1196 1197 main_timer15: timer@24f0000 { 1198 compatible = "ti,am654-timer"; 1199 reg = <0x00 0x24f0000 0x00 0x400>; 1200 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&k3_clks 66 1>; 1202 clock-names = "fck"; 1203 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; 1204 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; 1205 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1206 ti,timer-pwm; 1207 }; 1208 1209 main_timer16: timer@2500000 { 1210 compatible = "ti,am654-timer"; 1211 reg = <0x00 0x2500000 0x00 0x400>; 1212 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&k3_clks 67 1>; 1214 clock-names = "fck"; 1215 assigned-clocks = <&k3_clks 67 1>; 1216 assigned-clock-parents = <&k3_clks 67 2>; 1217 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1218 ti,timer-pwm; 1219 }; 1220 1221 main_timer17: timer@2510000 { 1222 compatible = "ti,am654-timer"; 1223 reg = <0x00 0x2510000 0x00 0x400>; 1224 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&k3_clks 68 1>; 1226 clock-names = "fck"; 1227 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; 1228 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; 1229 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1230 ti,timer-pwm; 1231 }; 1232 1233 main_timer18: timer@2520000 { 1234 compatible = "ti,am654-timer"; 1235 reg = <0x00 0x2520000 0x00 0x400>; 1236 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&k3_clks 69 1>; 1238 clock-names = "fck"; 1239 assigned-clocks = <&k3_clks 69 1>; 1240 assigned-clock-parents = <&k3_clks 69 2>; 1241 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1242 ti,timer-pwm; 1243 }; 1244 1245 main_timer19: timer@2530000 { 1246 compatible = "ti,am654-timer"; 1247 reg = <0x00 0x2530000 0x00 0x400>; 1248 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&k3_clks 70 1>; 1250 clock-names = "fck"; 1251 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; 1252 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; 1253 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1254 ti,timer-pwm; 1255 }; 1256 1257 main_r5fss0: r5fss@5c00000 { 1258 compatible = "ti,j7200-r5fss"; 1259 ti,cluster-mode = <1>; 1260 #address-cells = <1>; 1261 #size-cells = <1>; 1262 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 1263 <0x5d00000 0x00 0x5d00000 0x20000>; 1264 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 1265 1266 main_r5fss0_core0: r5f@5c00000 { 1267 compatible = "ti,j7200-r5f"; 1268 reg = <0x5c00000 0x00010000>, 1269 <0x5c10000 0x00010000>; 1270 reg-names = "atcm", "btcm"; 1271 ti,sci = <&dmsc>; 1272 ti,sci-dev-id = <245>; 1273 ti,sci-proc-ids = <0x06 0xff>; 1274 resets = <&k3_reset 245 1>; 1275 firmware-name = "j7200-main-r5f0_0-fw"; 1276 ti,atcm-enable = <1>; 1277 ti,btcm-enable = <1>; 1278 ti,loczrama = <1>; 1279 }; 1280 1281 main_r5fss0_core1: r5f@5d00000 { 1282 compatible = "ti,j7200-r5f"; 1283 reg = <0x5d00000 0x00008000>, 1284 <0x5d10000 0x00008000>; 1285 reg-names = "atcm", "btcm"; 1286 ti,sci = <&dmsc>; 1287 ti,sci-dev-id = <246>; 1288 ti,sci-proc-ids = <0x07 0xff>; 1289 resets = <&k3_reset 246 1>; 1290 firmware-name = "j7200-main-r5f0_1-fw"; 1291 ti,atcm-enable = <1>; 1292 ti,btcm-enable = <1>; 1293 ti,loczrama = <1>; 1294 }; 1295 }; 1296 1297 main_esm: esm@700000 { 1298 compatible = "ti,j721e-esm"; 1299 reg = <0x0 0x700000 0x0 0x1000>; 1300 ti,esm-pins = <656>, <657>; 1301 }; 1302}; 1303