1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 22 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 23 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 #interrupt-cells = <3>; 28 interrupt-controller; 29 /* 30 * vcpumntirq: 31 * virtual CPU interface maintenance interrupt 32 */ 33 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 35 gic_its: msi-controller@1820000 { 36 compatible = "arm,gic-v3-its"; 37 reg = <0x00 0x01820000 0x00 0x10000>; 38 socionext,synquacer-pre-its = <0x1000000 0x400000>; 39 msi-controller; 40 #msi-cells = <1>; 41 }; 42 }; 43 44 main_conf: syscon@100000 { 45 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 46 reg = <0x00 0x00100000 0x00 0x20000>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges = <0x00 0x00 0x00100000 0x20000>; 50 51 phy_gmii_sel: phy@4044 { 52 compatible = "ti,am654-phy-gmii-sel"; 53 reg = <0x4044 0x8>; 54 #phy-cells = <1>; 55 }; 56 57 epwm_tbclk: clock-controller@4130 { 58 compatible = "ti,am62-epwm-tbclk"; 59 reg = <0x4130 0x4>; 60 #clock-cells = <1>; 61 }; 62 }; 63 64 dmss: bus@48000000 { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 dma-ranges; 69 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 70 71 ti,sci-dev-id = <25>; 72 73 secure_proxy_main: mailbox@4d000000 { 74 compatible = "ti,am654-secure-proxy"; 75 reg = <0x00 0x4d000000 0x00 0x80000>, 76 <0x00 0x4a600000 0x00 0x80000>, 77 <0x00 0x4a400000 0x00 0x80000>; 78 reg-names = "target_data", "rt", "scfg"; 79 #mbox-cells = <1>; 80 interrupt-names = "rx_012"; 81 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 82 }; 83 84 inta_main_dmss: interrupt-controller@48000000 { 85 compatible = "ti,sci-inta"; 86 reg = <0x00 0x48000000 0x00 0x100000>; 87 #interrupt-cells = <0>; 88 interrupt-controller; 89 interrupt-parent = <&gic500>; 90 msi-controller; 91 ti,sci = <&dmsc>; 92 ti,sci-dev-id = <28>; 93 ti,interrupt-ranges = <6 70 34>; 94 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 95 }; 96 97 main_bcdma: dma-controller@485c0100 { 98 compatible = "ti,am64-dmss-bcdma"; 99 reg = <0x00 0x485c0100 0x00 0x100>, 100 <0x00 0x4c000000 0x00 0x20000>, 101 <0x00 0x4a820000 0x00 0x20000>, 102 <0x00 0x4aa40000 0x00 0x20000>, 103 <0x00 0x4bc00000 0x00 0x100000>; 104 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 105 msi-parent = <&inta_main_dmss>; 106 #dma-cells = <3>; 107 ti,sci = <&dmsc>; 108 ti,sci-dev-id = <26>; 109 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 110 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 111 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 112 }; 113 114 main_pktdma: dma-controller@485c0000 { 115 compatible = "ti,am64-dmss-pktdma"; 116 reg = <0x00 0x485c0000 0x00 0x100>, 117 <0x00 0x4a800000 0x00 0x20000>, 118 <0x00 0x4aa00000 0x00 0x40000>, 119 <0x00 0x4b800000 0x00 0x400000>; 120 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 121 msi-parent = <&inta_main_dmss>; 122 #dma-cells = <2>; 123 ti,sci = <&dmsc>; 124 ti,sci-dev-id = <30>; 125 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 126 <0x24>, /* CPSW_TX_CHAN */ 127 <0x25>, /* SAUL_TX_0_CHAN */ 128 <0x26>; /* SAUL_TX_1_CHAN */ 129 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 130 <0x11>, /* RING_CPSW_TX_CHAN */ 131 <0x12>, /* RING_SAUL_TX_0_CHAN */ 132 <0x13>; /* RING_SAUL_TX_1_CHAN */ 133 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 134 <0x2b>, /* CPSW_RX_CHAN */ 135 <0x2d>, /* SAUL_RX_0_CHAN */ 136 <0x2f>, /* SAUL_RX_1_CHAN */ 137 <0x31>, /* SAUL_RX_2_CHAN */ 138 <0x33>; /* SAUL_RX_3_CHAN */ 139 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 140 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 141 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 142 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 143 }; 144 }; 145 146 dmsc: system-controller@44043000 { 147 compatible = "ti,k2g-sci"; 148 reg = <0x00 0x44043000 0x00 0xfe0>; 149 reg-names = "debug_messages"; 150 ti,host-id = <12>; 151 mbox-names = "rx", "tx"; 152 mboxes = <&secure_proxy_main 12>, 153 <&secure_proxy_main 13>; 154 155 k3_pds: power-controller { 156 compatible = "ti,sci-pm-domain"; 157 #power-domain-cells = <2>; 158 }; 159 160 k3_clks: clock-controller { 161 compatible = "ti,k2g-sci-clk"; 162 #clock-cells = <2>; 163 }; 164 165 k3_reset: reset-controller { 166 compatible = "ti,sci-reset"; 167 #reset-cells = <2>; 168 }; 169 }; 170 171 secure_proxy_sa3: mailbox@43600000 { 172 compatible = "ti,am654-secure-proxy"; 173 #mbox-cells = <1>; 174 reg-names = "target_data", "rt", "scfg"; 175 reg = <0x00 0x43600000 0x00 0x10000>, 176 <0x00 0x44880000 0x00 0x20000>, 177 <0x00 0x44860000 0x00 0x20000>; 178 /* 179 * Marked Disabled: 180 * Node is incomplete as it is meant for bootloaders and 181 * firmware on non-MPU processors 182 */ 183 status = "disabled"; 184 }; 185 186 main_pmx0: pinctrl@f4000 { 187 compatible = "pinctrl-single"; 188 reg = <0x00 0xf4000 0x00 0x2ac>; 189 #pinctrl-cells = <1>; 190 pinctrl-single,register-width = <32>; 191 pinctrl-single,function-mask = <0xffffffff>; 192 }; 193 194 main_timer0: timer@2400000 { 195 compatible = "ti,am654-timer"; 196 reg = <0x00 0x2400000 0x00 0x400>; 197 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&k3_clks 36 2>; 199 clock-names = "fck"; 200 assigned-clocks = <&k3_clks 36 2>; 201 assigned-clock-parents = <&k3_clks 36 3>; 202 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 203 ti,timer-pwm; 204 }; 205 206 main_timer1: timer@2410000 { 207 compatible = "ti,am654-timer"; 208 reg = <0x00 0x2410000 0x00 0x400>; 209 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&k3_clks 37 2>; 211 clock-names = "fck"; 212 assigned-clocks = <&k3_clks 37 2>; 213 assigned-clock-parents = <&k3_clks 37 3>; 214 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 215 ti,timer-pwm; 216 }; 217 218 main_timer2: timer@2420000 { 219 compatible = "ti,am654-timer"; 220 reg = <0x00 0x2420000 0x00 0x400>; 221 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&k3_clks 38 2>; 223 clock-names = "fck"; 224 assigned-clocks = <&k3_clks 38 2>; 225 assigned-clock-parents = <&k3_clks 38 3>; 226 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 227 ti,timer-pwm; 228 }; 229 230 main_timer3: timer@2430000 { 231 compatible = "ti,am654-timer"; 232 reg = <0x00 0x2430000 0x00 0x400>; 233 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&k3_clks 39 2>; 235 clock-names = "fck"; 236 assigned-clocks = <&k3_clks 39 2>; 237 assigned-clock-parents = <&k3_clks 39 3>; 238 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 239 ti,timer-pwm; 240 }; 241 242 main_timer4: timer@2440000 { 243 compatible = "ti,am654-timer"; 244 reg = <0x00 0x2440000 0x00 0x400>; 245 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&k3_clks 40 2>; 247 clock-names = "fck"; 248 assigned-clocks = <&k3_clks 40 2>; 249 assigned-clock-parents = <&k3_clks 40 3>; 250 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 251 ti,timer-pwm; 252 }; 253 254 main_timer5: timer@2450000 { 255 compatible = "ti,am654-timer"; 256 reg = <0x00 0x2450000 0x00 0x400>; 257 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&k3_clks 41 2>; 259 clock-names = "fck"; 260 assigned-clocks = <&k3_clks 41 2>; 261 assigned-clock-parents = <&k3_clks 41 3>; 262 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 263 ti,timer-pwm; 264 }; 265 266 main_timer6: timer@2460000 { 267 compatible = "ti,am654-timer"; 268 reg = <0x00 0x2460000 0x00 0x400>; 269 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&k3_clks 42 2>; 271 clock-names = "fck"; 272 assigned-clocks = <&k3_clks 42 2>; 273 assigned-clock-parents = <&k3_clks 42 3>; 274 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 275 ti,timer-pwm; 276 }; 277 278 main_timer7: timer@2470000 { 279 compatible = "ti,am654-timer"; 280 reg = <0x00 0x2470000 0x00 0x400>; 281 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&k3_clks 43 2>; 283 clock-names = "fck"; 284 assigned-clocks = <&k3_clks 43 2>; 285 assigned-clock-parents = <&k3_clks 43 3>; 286 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 287 ti,timer-pwm; 288 }; 289 290 main_uart0: serial@2800000 { 291 compatible = "ti,am64-uart", "ti,am654-uart"; 292 reg = <0x00 0x02800000 0x00 0x100>; 293 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 294 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 295 clocks = <&k3_clks 146 0>; 296 clock-names = "fclk"; 297 status = "disabled"; 298 }; 299 300 main_uart1: serial@2810000 { 301 compatible = "ti,am64-uart", "ti,am654-uart"; 302 reg = <0x00 0x02810000 0x00 0x100>; 303 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 304 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 305 clocks = <&k3_clks 152 0>; 306 clock-names = "fclk"; 307 status = "disabled"; 308 }; 309 310 main_uart2: serial@2820000 { 311 compatible = "ti,am64-uart", "ti,am654-uart"; 312 reg = <0x00 0x02820000 0x00 0x100>; 313 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 314 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 315 clocks = <&k3_clks 153 0>; 316 clock-names = "fclk"; 317 status = "disabled"; 318 }; 319 320 main_uart3: serial@2830000 { 321 compatible = "ti,am64-uart", "ti,am654-uart"; 322 reg = <0x00 0x02830000 0x00 0x100>; 323 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 324 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 325 clocks = <&k3_clks 154 0>; 326 clock-names = "fclk"; 327 status = "disabled"; 328 }; 329 330 main_uart4: serial@2840000 { 331 compatible = "ti,am64-uart", "ti,am654-uart"; 332 reg = <0x00 0x02840000 0x00 0x100>; 333 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 334 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 335 clocks = <&k3_clks 155 0>; 336 clock-names = "fclk"; 337 status = "disabled"; 338 }; 339 340 main_uart5: serial@2850000 { 341 compatible = "ti,am64-uart", "ti,am654-uart"; 342 reg = <0x00 0x02850000 0x00 0x100>; 343 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 344 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 345 clocks = <&k3_clks 156 0>; 346 clock-names = "fclk"; 347 status = "disabled"; 348 }; 349 350 main_uart6: serial@2860000 { 351 compatible = "ti,am64-uart", "ti,am654-uart"; 352 reg = <0x00 0x02860000 0x00 0x100>; 353 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 354 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 355 clocks = <&k3_clks 158 0>; 356 clock-names = "fclk"; 357 status = "disabled"; 358 }; 359 360 main_i2c0: i2c@20000000 { 361 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 362 reg = <0x00 0x20000000 0x00 0x100>; 363 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 367 clocks = <&k3_clks 102 2>; 368 clock-names = "fck"; 369 status = "disabled"; 370 }; 371 372 main_i2c1: i2c@20010000 { 373 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 374 reg = <0x00 0x20010000 0x00 0x100>; 375 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 379 clocks = <&k3_clks 103 2>; 380 clock-names = "fck"; 381 status = "disabled"; 382 }; 383 384 main_i2c2: i2c@20020000 { 385 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 386 reg = <0x00 0x20020000 0x00 0x100>; 387 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 391 clocks = <&k3_clks 104 2>; 392 clock-names = "fck"; 393 status = "disabled"; 394 }; 395 396 main_i2c3: i2c@20030000 { 397 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 398 reg = <0x00 0x20030000 0x00 0x100>; 399 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 105 2>; 404 clock-names = "fck"; 405 status = "disabled"; 406 }; 407 408 main_spi0: spi@20100000 { 409 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 410 reg = <0x00 0x20100000 0x00 0x400>; 411 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 415 clocks = <&k3_clks 141 0>; 416 status = "disabled"; 417 }; 418 419 main_spi1: spi@20110000 { 420 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 421 reg = <0x00 0x20110000 0x00 0x400>; 422 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 142 0>; 427 status = "disabled"; 428 }; 429 430 main_spi2: spi@20120000 { 431 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 432 reg = <0x00 0x20120000 0x00 0x400>; 433 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 437 clocks = <&k3_clks 143 0>; 438 status = "disabled"; 439 }; 440 441 main_gpio_intr: interrupt-controller@a00000 { 442 compatible = "ti,sci-intr"; 443 reg = <0x00 0x00a00000 0x00 0x800>; 444 ti,intr-trigger-type = <1>; 445 interrupt-controller; 446 interrupt-parent = <&gic500>; 447 #interrupt-cells = <1>; 448 ti,sci = <&dmsc>; 449 ti,sci-dev-id = <3>; 450 ti,interrupt-ranges = <0 32 16>; 451 status = "disabled"; 452 }; 453 454 main_gpio0: gpio@600000 { 455 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 456 reg = <0x00 0x00600000 0x0 0x100>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-parent = <&main_gpio_intr>; 460 interrupts = <190>, <191>, <192>, 461 <193>, <194>, <195>; 462 interrupt-controller; 463 #interrupt-cells = <2>; 464 ti,ngpio = <92>; 465 ti,davinci-gpio-unbanked = <0>; 466 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 467 clocks = <&k3_clks 77 0>; 468 clock-names = "gpio"; 469 status = "disabled"; 470 }; 471 472 main_gpio1: gpio@601000 { 473 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 474 reg = <0x00 0x00601000 0x0 0x100>; 475 gpio-controller; 476 #gpio-cells = <2>; 477 interrupt-parent = <&main_gpio_intr>; 478 interrupts = <180>, <181>, <182>, 479 <183>, <184>, <185>; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 ti,ngpio = <52>; 483 ti,davinci-gpio-unbanked = <0>; 484 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 485 clocks = <&k3_clks 78 0>; 486 clock-names = "gpio"; 487 status = "disabled"; 488 }; 489 490 sdhci1: mmc@fa00000 { 491 compatible = "ti,am62-sdhci"; 492 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 494 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 495 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 496 clock-names = "clk_ahb", "clk_xin"; 497 ti,trm-icp = <0x2>; 498 ti,otap-del-sel-legacy = <0x0>; 499 ti,otap-del-sel-sd-hs = <0x0>; 500 ti,otap-del-sel-sdr12 = <0xf>; 501 ti,otap-del-sel-sdr25 = <0xf>; 502 ti,otap-del-sel-sdr50 = <0xc>; 503 ti,otap-del-sel-sdr104 = <0x6>; 504 ti,otap-del-sel-ddr50 = <0x9>; 505 ti,itap-del-sel-legacy = <0x0>; 506 ti,itap-del-sel-sd-hs = <0x0>; 507 ti,itap-del-sel-sdr12 = <0x0>; 508 ti,itap-del-sel-sdr25 = <0x0>; 509 ti,clkbuf-sel = <0x7>; 510 bus-width = <4>; 511 no-1-8-v; 512 status = "disabled"; 513 }; 514 515 usbss0: dwc3-usb@f900000 { 516 compatible = "ti,am62-usb"; 517 reg = <0x00 0x0f900000 0x00 0x800>; 518 clocks = <&k3_clks 161 3>; 519 clock-names = "ref"; 520 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 521 #address-cells = <2>; 522 #size-cells = <2>; 523 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 524 ranges; 525 status = "disabled"; 526 527 usb0: usb@31000000 { 528 compatible = "snps,dwc3"; 529 reg = <0x00 0x31000000 0x00 0x50000>; 530 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 531 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 532 interrupt-names = "host", "peripheral"; 533 maximum-speed = "high-speed"; 534 dr_mode = "otg"; 535 }; 536 }; 537 538 usbss1: dwc3-usb@f910000 { 539 compatible = "ti,am62-usb"; 540 reg = <0x00 0x0f910000 0x00 0x800>; 541 clocks = <&k3_clks 162 3>; 542 clock-names = "ref"; 543 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 544 #address-cells = <2>; 545 #size-cells = <2>; 546 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 547 ranges; 548 status = "disabled"; 549 550 usb1: usb@31100000 { 551 compatible = "snps,dwc3"; 552 reg = <0x00 0x31100000 0x00 0x50000>; 553 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 554 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 555 interrupt-names = "host", "peripheral"; 556 maximum-speed = "high-speed"; 557 dr_mode = "otg"; 558 }; 559 }; 560 561 fss: bus@fc00000 { 562 compatible = "simple-bus"; 563 reg = <0x00 0x0fc00000 0x00 0x70000>; 564 #address-cells = <2>; 565 #size-cells = <2>; 566 ranges; 567 status = "disabled"; 568 569 ospi0: spi@fc40000 { 570 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 571 reg = <0x00 0x0fc40000 0x00 0x100>, 572 <0x05 0x00000000 0x01 0x00000000>; 573 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 574 cdns,fifo-depth = <256>; 575 cdns,fifo-width = <4>; 576 cdns,trigger-address = <0x0>; 577 clocks = <&k3_clks 75 7>; 578 assigned-clocks = <&k3_clks 75 7>; 579 assigned-clock-parents = <&k3_clks 75 8>; 580 assigned-clock-rates = <166666666>; 581 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 }; 585 }; 586 587 cpsw3g: ethernet@8000000 { 588 compatible = "ti,am642-cpsw-nuss"; 589 #address-cells = <2>; 590 #size-cells = <2>; 591 reg = <0x0 0x8000000 0x0 0x200000>; 592 reg-names = "cpsw_nuss"; 593 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 594 clocks = <&k3_clks 13 0>; 595 assigned-clocks = <&k3_clks 13 3>; 596 assigned-clock-parents = <&k3_clks 13 11>; 597 clock-names = "fck"; 598 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 599 status = "disabled"; 600 601 dmas = <&main_pktdma 0xc600 15>, 602 <&main_pktdma 0xc601 15>, 603 <&main_pktdma 0xc602 15>, 604 <&main_pktdma 0xc603 15>, 605 <&main_pktdma 0xc604 15>, 606 <&main_pktdma 0xc605 15>, 607 <&main_pktdma 0xc606 15>, 608 <&main_pktdma 0xc607 15>, 609 <&main_pktdma 0x4600 15>; 610 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 611 "tx7", "rx"; 612 613 ethernet-ports { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 617 cpsw_port1: port@1 { 618 reg = <1>; 619 ti,mac-only; 620 label = "port1"; 621 phys = <&phy_gmii_sel 1>; 622 mac-address = [00 00 00 00 00 00]; 623 ti,syscon-efuse = <&wkup_conf 0x200>; 624 }; 625 626 cpsw_port2: port@2 { 627 reg = <2>; 628 ti,mac-only; 629 label = "port2"; 630 phys = <&phy_gmii_sel 2>; 631 mac-address = [00 00 00 00 00 00]; 632 }; 633 }; 634 635 cpsw3g_mdio: mdio@f00 { 636 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 637 reg = <0x0 0xf00 0x0 0x100>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 clocks = <&k3_clks 13 0>; 641 clock-names = "fck"; 642 bus_freq = <1000000>; 643 }; 644 645 cpts@3d000 { 646 compatible = "ti,j721e-cpts"; 647 reg = <0x0 0x3d000 0x0 0x400>; 648 clocks = <&k3_clks 13 3>; 649 clock-names = "cpts"; 650 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "cpts"; 652 ti,cpts-ext-ts-inputs = <4>; 653 ti,cpts-periodic-outputs = <2>; 654 }; 655 }; 656 657 hwspinlock: spinlock@2a000000 { 658 compatible = "ti,am64-hwspinlock"; 659 reg = <0x00 0x2a000000 0x00 0x1000>; 660 #hwlock-cells = <1>; 661 }; 662 663 mailbox0_cluster0: mailbox@29000000 { 664 compatible = "ti,am64-mailbox"; 665 reg = <0x00 0x29000000 0x00 0x200>; 666 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 667 #mbox-cells = <1>; 668 ti,mbox-num-users = <4>; 669 ti,mbox-num-fifos = <16>; 670 }; 671 672 mailbox0_cluster1: mailbox@29010000 { 673 compatible = "ti,am64-mailbox"; 674 reg = <0x00 0x29010000 0x00 0x200>; 675 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 676 #mbox-cells = <1>; 677 ti,mbox-num-users = <4>; 678 ti,mbox-num-fifos = <16>; 679 }; 680 681 mailbox0_cluster2: mailbox@29020000 { 682 compatible = "ti,am64-mailbox"; 683 reg = <0x00 0x29020000 0x00 0x200>; 684 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 685 #mbox-cells = <1>; 686 ti,mbox-num-users = <4>; 687 ti,mbox-num-fifos = <16>; 688 }; 689 690 mailbox0_cluster3: mailbox@29030000 { 691 compatible = "ti,am64-mailbox"; 692 reg = <0x00 0x29030000 0x00 0x200>; 693 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 694 #mbox-cells = <1>; 695 ti,mbox-num-users = <4>; 696 ti,mbox-num-fifos = <16>; 697 }; 698 699 main_mcan0: can@20701000 { 700 compatible = "bosch,m_can"; 701 reg = <0x00 0x20701000 0x00 0x200>, 702 <0x00 0x20708000 0x00 0x8000>; 703 reg-names = "m_can", "message_ram"; 704 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 705 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 706 clock-names = "hclk", "cclk"; 707 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 709 interrupt-names = "int0", "int1"; 710 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 711 status = "disabled"; 712 }; 713 714 main_rti0: watchdog@e000000 { 715 compatible = "ti,j7-rti-wdt"; 716 reg = <0x00 0x0e000000 0x00 0x100>; 717 clocks = <&k3_clks 125 0>; 718 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 719 assigned-clocks = <&k3_clks 125 0>; 720 assigned-clock-parents = <&k3_clks 125 2>; 721 }; 722 723 main_rti1: watchdog@e010000 { 724 compatible = "ti,j7-rti-wdt"; 725 reg = <0x00 0x0e010000 0x00 0x100>; 726 clocks = <&k3_clks 126 0>; 727 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 728 assigned-clocks = <&k3_clks 126 0>; 729 assigned-clock-parents = <&k3_clks 126 2>; 730 }; 731 732 main_rti2: watchdog@e020000 { 733 compatible = "ti,j7-rti-wdt"; 734 reg = <0x00 0x0e020000 0x00 0x100>; 735 clocks = <&k3_clks 127 0>; 736 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 737 assigned-clocks = <&k3_clks 127 0>; 738 assigned-clock-parents = <&k3_clks 127 2>; 739 }; 740 741 main_rti3: watchdog@e030000 { 742 compatible = "ti,j7-rti-wdt"; 743 reg = <0x00 0x0e030000 0x00 0x100>; 744 clocks = <&k3_clks 128 0>; 745 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 746 assigned-clocks = <&k3_clks 128 0>; 747 assigned-clock-parents = <&k3_clks 128 2>; 748 }; 749 750 main_rti4: watchdog@e040000 { 751 compatible = "ti,j7-rti-wdt"; 752 reg = <0x00 0x0e040000 0x00 0x100>; 753 clocks = <&k3_clks 205 0>; 754 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; 755 assigned-clocks = <&k3_clks 205 0>; 756 assigned-clock-parents = <&k3_clks 205 2>; 757 }; 758 759 epwm0: pwm@23000000 { 760 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 761 #pwm-cells = <3>; 762 reg = <0x00 0x23000000 0x00 0x100>; 763 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 764 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 765 clock-names = "tbclk", "fck"; 766 status = "disabled"; 767 }; 768 769 epwm1: pwm@23010000 { 770 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 771 #pwm-cells = <3>; 772 reg = <0x00 0x23010000 0x00 0x100>; 773 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 774 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 775 clock-names = "tbclk", "fck"; 776 status = "disabled"; 777 }; 778 779 epwm2: pwm@23020000 { 780 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 781 #pwm-cells = <3>; 782 reg = <0x00 0x23020000 0x00 0x100>; 783 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 784 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 785 clock-names = "tbclk", "fck"; 786 status = "disabled"; 787 }; 788 789 ecap0: pwm@23100000 { 790 compatible = "ti,am3352-ecap"; 791 #pwm-cells = <3>; 792 reg = <0x00 0x23100000 0x00 0x100>; 793 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 794 clocks = <&k3_clks 51 0>; 795 clock-names = "fck"; 796 status = "disabled"; 797 }; 798 799 ecap1: pwm@23110000 { 800 compatible = "ti,am3352-ecap"; 801 #pwm-cells = <3>; 802 reg = <0x00 0x23110000 0x00 0x100>; 803 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 804 clocks = <&k3_clks 52 0>; 805 clock-names = "fck"; 806 status = "disabled"; 807 }; 808 809 ecap2: pwm@23120000 { 810 compatible = "ti,am3352-ecap"; 811 #pwm-cells = <3>; 812 reg = <0x00 0x23120000 0x00 0x100>; 813 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 814 clocks = <&k3_clks 53 0>; 815 clock-names = "fck"; 816 status = "disabled"; 817 }; 818}; 819