1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clocks { 21 sleep_clk: sleep-clk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 }; 25 26 xo_board_clk: xo-board-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a73"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq9574_s1>; 46 #cooling-cells = <2>; 47 }; 48 49 CPU1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a73"; 52 reg = <0x1>; 53 enable-method = "psci"; 54 next-level-cache = <&L2_0>; 55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 56 clock-names = "cpu"; 57 operating-points-v2 = <&cpu_opp_table>; 58 cpu-supply = <&ipq9574_s1>; 59 #cooling-cells = <2>; 60 }; 61 62 CPU2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a73"; 65 reg = <0x2>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 69 clock-names = "cpu"; 70 operating-points-v2 = <&cpu_opp_table>; 71 cpu-supply = <&ipq9574_s1>; 72 #cooling-cells = <2>; 73 }; 74 75 CPU3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a73"; 78 reg = <0x3>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_0>; 81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 82 clock-names = "cpu"; 83 operating-points-v2 = <&cpu_opp_table>; 84 cpu-supply = <&ipq9574_s1>; 85 #cooling-cells = <2>; 86 }; 87 88 L2_0: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 }; 93 }; 94 95 firmware { 96 scm { 97 compatible = "qcom,scm-ipq9574", "qcom,scm"; 98 qcom,dload-mode = <&tcsr 0x6100>; 99 }; 100 }; 101 102 memory@40000000 { 103 device_type = "memory"; 104 /* We expect the bootloader to fill in the size */ 105 reg = <0x0 0x40000000 0x0 0x0>; 106 }; 107 108 cpu_opp_table: opp-table-cpu { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-936000000 { 113 opp-hz = /bits/ 64 <936000000>; 114 opp-microvolt = <725000>; 115 clock-latency-ns = <200000>; 116 }; 117 118 opp-1104000000 { 119 opp-hz = /bits/ 64 <1104000000>; 120 opp-microvolt = <787500>; 121 clock-latency-ns = <200000>; 122 }; 123 124 opp-1416000000 { 125 opp-hz = /bits/ 64 <1416000000>; 126 opp-microvolt = <862500>; 127 clock-latency-ns = <200000>; 128 }; 129 130 opp-1488000000 { 131 opp-hz = /bits/ 64 <1488000000>; 132 opp-microvolt = <925000>; 133 clock-latency-ns = <200000>; 134 }; 135 136 opp-1800000000 { 137 opp-hz = /bits/ 64 <1800000000>; 138 opp-microvolt = <987500>; 139 clock-latency-ns = <200000>; 140 }; 141 142 opp-2208000000 { 143 opp-hz = /bits/ 64 <2208000000>; 144 opp-microvolt = <1062500>; 145 clock-latency-ns = <200000>; 146 }; 147 }; 148 149 pmu { 150 compatible = "arm,cortex-a73-pmu"; 151 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 152 }; 153 154 psci { 155 compatible = "arm,psci-1.0"; 156 method = "smc"; 157 }; 158 159 rpm: remoteproc { 160 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; 161 162 glink-edge { 163 compatible = "qcom,glink-rpm"; 164 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 165 qcom,rpm-msg-ram = <&rpm_msg_ram>; 166 mboxes = <&apcs_glb 0>; 167 168 rpm_requests: rpm-requests { 169 compatible = "qcom,rpm-ipq9574"; 170 qcom,glink-channels = "rpm_requests"; 171 }; 172 }; 173 }; 174 175 reserved-memory { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges; 179 180 bootloader@4a100000 { 181 reg = <0x0 0x4a100000 0x0 0x400000>; 182 no-map; 183 }; 184 185 sbl@4a500000 { 186 reg = <0x0 0x4a500000 0x0 0x100000>; 187 no-map; 188 }; 189 190 tz_region: tz@4a600000 { 191 reg = <0x0 0x4a600000 0x0 0x400000>; 192 no-map; 193 }; 194 195 smem@4aa00000 { 196 compatible = "qcom,smem"; 197 reg = <0x0 0x4aa00000 0x0 0x100000>; 198 hwlocks = <&tcsr_mutex 3>; 199 no-map; 200 }; 201 }; 202 203 soc: soc@0 { 204 compatible = "simple-bus"; 205 #address-cells = <1>; 206 #size-cells = <1>; 207 ranges = <0 0 0 0xffffffff>; 208 209 rpm_msg_ram: sram@60000 { 210 compatible = "qcom,rpm-msg-ram"; 211 reg = <0x00060000 0x6000>; 212 }; 213 214 rng: rng@e3000 { 215 compatible = "qcom,prng-ee"; 216 reg = <0x000e3000 0x1000>; 217 clocks = <&gcc GCC_PRNG_AHB_CLK>; 218 clock-names = "core"; 219 }; 220 221 qfprom: efuse@a4000 { 222 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 223 reg = <0x000a4000 0x5a1>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 }; 227 228 cryptobam: dma-controller@704000 { 229 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 230 reg = <0x00704000 0x20000>; 231 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 232 #dma-cells = <1>; 233 qcom,ee = <1>; 234 qcom,num-ees = <4>; 235 num-channels = <16>; 236 qcom,controlled-remotely; 237 }; 238 239 crypto: crypto@73a000 { 240 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 241 reg = <0x0073a000 0x6000>; 242 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 243 <&gcc GCC_CRYPTO_AXI_CLK>, 244 <&gcc GCC_CRYPTO_CLK>; 245 clock-names = "iface", "bus", "core"; 246 dmas = <&cryptobam 2>, <&cryptobam 3>; 247 dma-names = "rx", "tx"; 248 }; 249 250 tsens: thermal-sensor@4a9000 { 251 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 252 reg = <0x004a9000 0x1000>, 253 <0x004a8000 0x1000>; 254 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-names = "combined"; 256 #qcom,sensors = <16>; 257 #thermal-sensor-cells = <1>; 258 }; 259 260 tlmm: pinctrl@1000000 { 261 compatible = "qcom,ipq9574-tlmm"; 262 reg = <0x01000000 0x300000>; 263 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 264 gpio-controller; 265 #gpio-cells = <2>; 266 gpio-ranges = <&tlmm 0 0 65>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 270 uart2_pins: uart2-state { 271 pins = "gpio34", "gpio35"; 272 function = "blsp2_uart"; 273 drive-strength = <8>; 274 bias-disable; 275 }; 276 }; 277 278 gcc: clock-controller@1800000 { 279 compatible = "qcom,ipq9574-gcc"; 280 reg = <0x01800000 0x80000>; 281 clocks = <&xo_board_clk>, 282 <&sleep_clk>, 283 <0>, 284 <0>, 285 <0>, 286 <0>, 287 <0>, 288 <0>; 289 #clock-cells = <1>; 290 #reset-cells = <1>; 291 #power-domain-cells = <1>; 292 }; 293 294 tcsr_mutex: hwlock@1905000 { 295 compatible = "qcom,tcsr-mutex"; 296 reg = <0x01905000 0x20000>; 297 #hwlock-cells = <1>; 298 }; 299 300 tcsr: syscon@1937000 { 301 compatible = "qcom,tcsr-ipq9574", "syscon"; 302 reg = <0x01937000 0x21000>; 303 }; 304 305 sdhc_1: mmc@7804000 { 306 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 307 reg = <0x07804000 0x1000>, <0x07805000 0x1000>; 308 reg-names = "hc", "cqhci"; 309 310 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 312 interrupt-names = "hc_irq", "pwr_irq"; 313 314 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 315 <&gcc GCC_SDCC1_APPS_CLK>, 316 <&xo_board_clk>; 317 clock-names = "iface", "core", "xo"; 318 non-removable; 319 status = "disabled"; 320 }; 321 322 blsp_dma: dma-controller@7884000 { 323 compatible = "qcom,bam-v1.7.0"; 324 reg = <0x07884000 0x2b000>; 325 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 327 clock-names = "bam_clk"; 328 #dma-cells = <1>; 329 qcom,ee = <0>; 330 }; 331 332 blsp1_uart0: serial@78af000 { 333 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 334 reg = <0x078af000 0x200>; 335 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 337 <&gcc GCC_BLSP1_AHB_CLK>; 338 clock-names = "core", "iface"; 339 status = "disabled"; 340 }; 341 342 blsp1_uart1: serial@78b0000 { 343 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 344 reg = <0x078b0000 0x200>; 345 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 347 <&gcc GCC_BLSP1_AHB_CLK>; 348 clock-names = "core", "iface"; 349 status = "disabled"; 350 }; 351 352 blsp1_uart2: serial@78b1000 { 353 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 354 reg = <0x078b1000 0x200>; 355 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 357 <&gcc GCC_BLSP1_AHB_CLK>; 358 clock-names = "core", "iface"; 359 status = "disabled"; 360 }; 361 362 blsp1_uart3: serial@78b2000 { 363 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 364 reg = <0x078b2000 0x200>; 365 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 367 <&gcc GCC_BLSP1_AHB_CLK>; 368 clock-names = "core", "iface"; 369 status = "disabled"; 370 }; 371 372 blsp1_uart4: serial@78b3000 { 373 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 374 reg = <0x078b3000 0x200>; 375 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 377 <&gcc GCC_BLSP1_AHB_CLK>; 378 clock-names = "core", "iface"; 379 status = "disabled"; 380 }; 381 382 blsp1_uart5: serial@78b4000 { 383 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 384 reg = <0x078b4000 0x200>; 385 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 387 <&gcc GCC_BLSP1_AHB_CLK>; 388 clock-names = "core", "iface"; 389 status = "disabled"; 390 }; 391 392 blsp1_spi0: spi@78b5000 { 393 compatible = "qcom,spi-qup-v2.2.1"; 394 reg = <0x078b5000 0x600>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 399 <&gcc GCC_BLSP1_AHB_CLK>; 400 clock-names = "core", "iface"; 401 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 402 dma-names = "tx", "rx"; 403 status = "disabled"; 404 }; 405 406 blsp1_i2c1: i2c@78b6000 { 407 compatible = "qcom,i2c-qup-v2.2.1"; 408 reg = <0x078b6000 0x600>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 413 <&gcc GCC_BLSP1_AHB_CLK>; 414 clock-names = "core", "iface"; 415 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 416 assigned-clock-rates = <50000000>; 417 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 418 dma-names = "tx", "rx"; 419 status = "disabled"; 420 }; 421 422 blsp1_spi1: spi@78b6000 { 423 compatible = "qcom,spi-qup-v2.2.1"; 424 reg = <0x078b6000 0x600>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 429 <&gcc GCC_BLSP1_AHB_CLK>; 430 clock-names = "core", "iface"; 431 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 432 dma-names = "tx", "rx"; 433 status = "disabled"; 434 }; 435 436 blsp1_i2c2: i2c@78b7000 { 437 compatible = "qcom,i2c-qup-v2.2.1"; 438 reg = <0x078b7000 0x600>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 443 <&gcc GCC_BLSP1_AHB_CLK>; 444 clock-names = "core", "iface"; 445 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 446 assigned-clock-rates = <50000000>; 447 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 448 dma-names = "tx", "rx"; 449 status = "disabled"; 450 }; 451 452 blsp1_spi2: spi@78b7000 { 453 compatible = "qcom,spi-qup-v2.2.1"; 454 reg = <0x078b7000 0x600>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 459 <&gcc GCC_BLSP1_AHB_CLK>; 460 clock-names = "core", "iface"; 461 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 462 dma-names = "tx", "rx"; 463 status = "disabled"; 464 }; 465 466 blsp1_i2c3: i2c@78b8000 { 467 compatible = "qcom,i2c-qup-v2.2.1"; 468 reg = <0x078b8000 0x600>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 473 <&gcc GCC_BLSP1_AHB_CLK>; 474 clock-names = "core", "iface"; 475 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 476 assigned-clock-rates = <50000000>; 477 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 478 dma-names = "tx", "rx"; 479 status = "disabled"; 480 }; 481 482 blsp1_spi3: spi@78b8000 { 483 compatible = "qcom,spi-qup-v2.2.1"; 484 reg = <0x078b8000 0x600>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 488 spi-max-frequency = <50000000>; 489 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 490 <&gcc GCC_BLSP1_AHB_CLK>; 491 clock-names = "core", "iface"; 492 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 493 dma-names = "tx", "rx"; 494 status = "disabled"; 495 }; 496 497 blsp1_i2c4: i2c@78b9000 { 498 compatible = "qcom,i2c-qup-v2.2.1"; 499 reg = <0x078b9000 0x600>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 504 <&gcc GCC_BLSP1_AHB_CLK>; 505 clock-names = "core", "iface"; 506 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 507 assigned-clock-rates = <50000000>; 508 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 509 dma-names = "tx", "rx"; 510 status = "disabled"; 511 }; 512 513 blsp1_spi4: spi@78b9000 { 514 compatible = "qcom,spi-qup-v2.2.1"; 515 reg = <0x078b9000 0x600>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 520 <&gcc GCC_BLSP1_AHB_CLK>; 521 clock-names = "core", "iface"; 522 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 523 dma-names = "tx", "rx"; 524 status = "disabled"; 525 }; 526 527 usb_0_qusbphy: phy@7b000 { 528 compatible = "qcom,ipq9574-qusb2-phy"; 529 reg = <0x0007b000 0x180>; 530 #phy-cells = <0>; 531 532 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 533 <&xo_board_clk>; 534 clock-names = "cfg_ahb", 535 "ref"; 536 537 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 538 status = "disabled"; 539 }; 540 541 usb_0_qmpphy: phy@7d000 { 542 compatible = "qcom,ipq9574-qmp-usb3-phy"; 543 reg = <0x0007d000 0xa00>; 544 #phy-cells = <0>; 545 546 clocks = <&gcc GCC_USB0_AUX_CLK>, 547 <&xo_board_clk>, 548 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 549 <&gcc GCC_USB0_PIPE_CLK>; 550 clock-names = "aux", 551 "ref", 552 "cfg_ahb", 553 "pipe"; 554 555 resets = <&gcc GCC_USB0_PHY_BCR>, 556 <&gcc GCC_USB3PHY_0_PHY_BCR>; 557 reset-names = "phy", 558 "phy_phy"; 559 560 #clock-cells = <0>; 561 clock-output-names = "usb0_pipe_clk"; 562 563 status = "disabled"; 564 }; 565 566 usb3: usb@8af8800 { 567 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; 568 reg = <0x08af8800 0x400>; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges; 572 573 clocks = <&gcc GCC_SNOC_USB_CLK>, 574 <&gcc GCC_USB0_MASTER_CLK>, 575 <&gcc GCC_ANOC_USB_AXI_CLK>, 576 <&gcc GCC_USB0_SLEEP_CLK>, 577 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 578 579 clock-names = "cfg_noc", 580 "core", 581 "iface", 582 "sleep", 583 "mock_utmi"; 584 585 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 586 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 587 assigned-clock-rates = <200000000>, 588 <24000000>; 589 590 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "pwr_event"; 592 593 resets = <&gcc GCC_USB_BCR>; 594 status = "disabled"; 595 596 usb_0_dwc3: usb@8a00000 { 597 compatible = "snps,dwc3"; 598 reg = <0x8a00000 0xcd00>; 599 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 600 clock-names = "ref"; 601 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 602 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; 603 phy-names = "usb2-phy", "usb3-phy"; 604 tx-fifo-resize; 605 snps,is-utmi-l1-suspend; 606 snps,hird-threshold = /bits/ 8 <0x0>; 607 snps,dis_u2_susphy_quirk; 608 snps,dis_u3_susphy_quirk; 609 }; 610 }; 611 612 intc: interrupt-controller@b000000 { 613 compatible = "qcom,msm-qgic2"; 614 reg = <0x0b000000 0x1000>, /* GICD */ 615 <0x0b002000 0x2000>, /* GICC */ 616 <0x0b001000 0x1000>, /* GICH */ 617 <0x0b004000 0x2000>; /* GICV */ 618 #address-cells = <1>; 619 #size-cells = <1>; 620 interrupt-controller; 621 #interrupt-cells = <3>; 622 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 623 ranges = <0 0x0b00c000 0x3000>; 624 625 v2m0: v2m@0 { 626 compatible = "arm,gic-v2m-frame"; 627 reg = <0x00000000 0xffd>; 628 msi-controller; 629 }; 630 631 v2m1: v2m@1000 { 632 compatible = "arm,gic-v2m-frame"; 633 reg = <0x00001000 0xffd>; 634 msi-controller; 635 }; 636 637 v2m2: v2m@2000 { 638 compatible = "arm,gic-v2m-frame"; 639 reg = <0x00002000 0xffd>; 640 msi-controller; 641 }; 642 }; 643 644 watchdog: watchdog@b017000 { 645 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 646 reg = <0x0b017000 0x1000>; 647 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 648 clocks = <&sleep_clk>; 649 timeout-sec = <30>; 650 }; 651 652 apcs_glb: mailbox@b111000 { 653 compatible = "qcom,ipq9574-apcs-apps-global", 654 "qcom,ipq6018-apcs-apps-global"; 655 reg = <0x0b111000 0x1000>; 656 #clock-cells = <1>; 657 clocks = <&a73pll>, <&xo_board_clk>; 658 clock-names = "pll", "xo"; 659 #mbox-cells = <1>; 660 }; 661 662 a73pll: clock@b116000 { 663 compatible = "qcom,ipq9574-a73pll"; 664 reg = <0x0b116000 0x40>; 665 #clock-cells = <0>; 666 clocks = <&xo_board_clk>; 667 clock-names = "xo"; 668 }; 669 670 timer@b120000 { 671 compatible = "arm,armv7-timer-mem"; 672 reg = <0x0b120000 0x1000>; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 ranges; 676 677 frame@b120000 { 678 reg = <0x0b121000 0x1000>, 679 <0x0b122000 0x1000>; 680 frame-number = <0>; 681 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 683 }; 684 685 frame@b123000 { 686 reg = <0x0b123000 0x1000>; 687 frame-number = <1>; 688 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 689 status = "disabled"; 690 }; 691 692 frame@b124000 { 693 reg = <0x0b124000 0x1000>; 694 frame-number = <2>; 695 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 696 status = "disabled"; 697 }; 698 699 frame@b125000 { 700 reg = <0x0b125000 0x1000>; 701 frame-number = <3>; 702 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 703 status = "disabled"; 704 }; 705 706 frame@b126000 { 707 reg = <0x0b126000 0x1000>; 708 frame-number = <4>; 709 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 710 status = "disabled"; 711 }; 712 713 frame@b127000 { 714 reg = <0x0b127000 0x1000>; 715 frame-number = <5>; 716 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 717 status = "disabled"; 718 }; 719 720 frame@b128000 { 721 reg = <0x0b128000 0x1000>; 722 frame-number = <6>; 723 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 724 status = "disabled"; 725 }; 726 }; 727 }; 728 729 thermal-zones { 730 nss-top-thermal { 731 polling-delay-passive = <0>; 732 polling-delay = <0>; 733 thermal-sensors = <&tsens 3>; 734 735 trips { 736 nss-top-critical { 737 temperature = <125000>; 738 hysteresis = <1000>; 739 type = "critical"; 740 }; 741 }; 742 }; 743 744 ubi-0-thermal { 745 polling-delay-passive = <0>; 746 polling-delay = <0>; 747 thermal-sensors = <&tsens 4>; 748 749 trips { 750 ubi_0-critical { 751 temperature = <125000>; 752 hysteresis = <1000>; 753 type = "critical"; 754 }; 755 }; 756 }; 757 758 ubi-1-thermal { 759 polling-delay-passive = <0>; 760 polling-delay = <0>; 761 thermal-sensors = <&tsens 5>; 762 763 trips { 764 ubi_1-critical { 765 temperature = <125000>; 766 hysteresis = <1000>; 767 type = "critical"; 768 }; 769 }; 770 }; 771 772 ubi-2-thermal { 773 polling-delay-passive = <0>; 774 polling-delay = <0>; 775 thermal-sensors = <&tsens 6>; 776 777 trips { 778 ubi_2-critical { 779 temperature = <125000>; 780 hysteresis = <1000>; 781 type = "critical"; 782 }; 783 }; 784 }; 785 786 ubi-3-thermal { 787 polling-delay-passive = <0>; 788 polling-delay = <0>; 789 thermal-sensors = <&tsens 7>; 790 791 trips { 792 ubi_3-critical { 793 temperature = <125000>; 794 hysteresis = <1000>; 795 type = "critical"; 796 }; 797 }; 798 }; 799 800 cpuss0-thermal { 801 polling-delay-passive = <0>; 802 polling-delay = <0>; 803 thermal-sensors = <&tsens 8>; 804 805 trips { 806 cpu-critical { 807 temperature = <125000>; 808 hysteresis = <1000>; 809 type = "critical"; 810 }; 811 }; 812 }; 813 814 cpuss1-thermal { 815 polling-delay-passive = <0>; 816 polling-delay = <0>; 817 thermal-sensors = <&tsens 9>; 818 819 trips { 820 cpu-critical { 821 temperature = <125000>; 822 hysteresis = <1000>; 823 type = "critical"; 824 }; 825 }; 826 }; 827 828 cpu0-thermal { 829 polling-delay-passive = <0>; 830 polling-delay = <0>; 831 thermal-sensors = <&tsens 10>; 832 833 trips { 834 cpu0_crit: cpu-critical { 835 temperature = <120000>; 836 hysteresis = <10000>; 837 type = "critical"; 838 }; 839 840 cpu0_alert: cpu-passive { 841 temperature = <110000>; 842 hysteresis = <1000>; 843 type = "passive"; 844 }; 845 }; 846 847 cooling-maps { 848 map0 { 849 trip = <&cpu0_alert>; 850 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 851 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 852 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 853 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 854 }; 855 }; 856 }; 857 858 cpu1-thermal { 859 polling-delay-passive = <0>; 860 polling-delay = <0>; 861 thermal-sensors = <&tsens 11>; 862 863 trips { 864 cpu1_crit: cpu-critical { 865 temperature = <120000>; 866 hysteresis = <10000>; 867 type = "critical"; 868 }; 869 870 cpu1_alert: cpu-passive { 871 temperature = <110000>; 872 hysteresis = <1000>; 873 type = "passive"; 874 }; 875 }; 876 877 cooling-maps { 878 map0 { 879 trip = <&cpu1_alert>; 880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 881 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 882 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 883 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 884 }; 885 }; 886 }; 887 888 cpu2-thermal { 889 polling-delay-passive = <0>; 890 polling-delay = <0>; 891 thermal-sensors = <&tsens 12>; 892 893 trips { 894 cpu2_crit: cpu-critical { 895 temperature = <120000>; 896 hysteresis = <10000>; 897 type = "critical"; 898 }; 899 900 cpu2_alert: cpu-passive { 901 temperature = <110000>; 902 hysteresis = <1000>; 903 type = "passive"; 904 }; 905 }; 906 907 cooling-maps { 908 map0 { 909 trip = <&cpu2_alert>; 910 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 911 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 912 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 913 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 914 }; 915 }; 916 }; 917 918 cpu3-thermal { 919 polling-delay-passive = <0>; 920 polling-delay = <0>; 921 thermal-sensors = <&tsens 13>; 922 923 trips { 924 cpu3_crit: cpu-critical { 925 temperature = <120000>; 926 hysteresis = <10000>; 927 type = "critical"; 928 }; 929 930 cpu3_alert: cpu-passive { 931 temperature = <110000>; 932 hysteresis = <1000>; 933 type = "passive"; 934 }; 935 }; 936 937 cooling-maps { 938 map0 { 939 trip = <&cpu3_alert>; 940 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 941 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 942 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 943 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 944 }; 945 }; 946 }; 947 948 wcss-phyb-thermal { 949 polling-delay-passive = <0>; 950 polling-delay = <0>; 951 thermal-sensors = <&tsens 14>; 952 953 trips { 954 wcss_phyb-critical { 955 temperature = <125000>; 956 hysteresis = <1000>; 957 type = "critical"; 958 }; 959 }; 960 }; 961 962 top-glue-thermal { 963 polling-delay-passive = <0>; 964 polling-delay = <0>; 965 thermal-sensors = <&tsens 15>; 966 967 trips { 968 top_glue-critical { 969 temperature = <125000>; 970 hysteresis = <1000>; 971 type = "critical"; 972 }; 973 }; 974 }; 975 }; 976 977 timer { 978 compatible = "arm,armv8-timer"; 979 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 980 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 981 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 982 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 983 }; 984}; 985