1/* 2 * RISC-V translation routines for the Control-Flow Integrity Extension 3 * 4 * Copyright (c) 2024 Rivos Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19#define REQUIRE_ZICFISS(ctx) do { \ 20 if (!ctx->cfg_ptr->ext_zicfiss) { \ 21 return false; \ 22 } \ 23} while (0) 24 25static bool trans_sspopchk(DisasContext *ctx, arg_sspopchk *a) 26{ 27 if (!ctx->bcfi_enabled) { 28 return false; 29 } 30 31 TCGv addr = tcg_temp_new(); 32 TCGLabel *skip = gen_new_label(); 33 uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4; 34 TCGv data = tcg_temp_new(); 35 tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); 36 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 37 tcg_gen_qemu_ld_tl(data, addr, SS_MMU_INDEX(ctx), 38 mxl_memop(ctx) | MO_ALIGN); 39 TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); 40 tcg_gen_brcond_tl(TCG_COND_EQ, data, rs1, skip); 41 tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_BCFI_TVAL), 42 tcg_env, offsetof(CPURISCVState, sw_check_code)); 43 gen_helper_raise_exception(tcg_env, 44 tcg_constant_i32(RISCV_EXCP_SW_CHECK)); 45 gen_set_label(skip); 46 tcg_gen_addi_tl(addr, addr, tmp); 47 tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); 48 49 return true; 50} 51 52static bool trans_sspush(DisasContext *ctx, arg_sspush *a) 53{ 54 if (!ctx->bcfi_enabled) { 55 return false; 56 } 57 58 TCGv addr = tcg_temp_new(); 59 int tmp = (get_xl(ctx) == MXL_RV64) ? -8 : -4; 60 TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); 61 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 62 tcg_gen_ld_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); 63 tcg_gen_addi_tl(addr, addr, tmp); 64 tcg_gen_qemu_st_tl(data, addr, SS_MMU_INDEX(ctx), 65 mxl_memop(ctx) | MO_ALIGN); 66 tcg_gen_st_tl(addr, tcg_env, offsetof(CPURISCVState, ssp)); 67 68 return true; 69} 70 71static bool trans_ssrdp(DisasContext *ctx, arg_ssrdp *a) 72{ 73 if (!ctx->bcfi_enabled || a->rd == 0) { 74 return false; 75 } 76 77 TCGv dest = dest_gpr(ctx, a->rd); 78 tcg_gen_ld_tl(dest, tcg_env, offsetof(CPURISCVState, ssp)); 79 gen_set_gpr(ctx, a->rd, dest); 80 81 return true; 82} 83 84static bool trans_ssamoswap_w(DisasContext *ctx, arg_amoswap_w *a) 85{ 86 REQUIRE_A_OR_ZAAMO(ctx); 87 REQUIRE_ZICFISS(ctx); 88 if (ctx->priv == PRV_M) { 89 generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT); 90 } 91 92 if (!ctx->bcfi_enabled) { 93 return false; 94 } 95 96 TCGv dest = dest_gpr(ctx, a->rd); 97 TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); 98 99 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 100 src1 = get_address(ctx, a->rs1, 0); 101 102 tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), 103 (MO_ALIGN | MO_TESL)); 104 gen_set_gpr(ctx, a->rd, dest); 105 return true; 106} 107 108static bool trans_ssamoswap_d(DisasContext *ctx, arg_amoswap_w *a) 109{ 110 REQUIRE_64BIT(ctx); 111 REQUIRE_A_OR_ZAAMO(ctx); 112 REQUIRE_ZICFISS(ctx); 113 if (ctx->priv == PRV_M) { 114 generate_exception(ctx, RISCV_EXCP_STORE_AMO_ACCESS_FAULT); 115 } 116 117 if (!ctx->bcfi_enabled) { 118 return false; 119 } 120 121 TCGv dest = dest_gpr(ctx, a->rd); 122 TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); 123 124 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 125 src1 = get_address(ctx, a->rs1, 0); 126 127 tcg_gen_atomic_xchg_tl(dest, src1, src2, SS_MMU_INDEX(ctx), 128 (MO_ALIGN | MO_TESQ)); 129 gen_set_gpr(ctx, a->rd, dest); 130 return true; 131} 132