1&l4_cfg { /* 0x4a000000 */ 2 compatible = "ti,dra7-l4-cfg", "simple-pm-bus"; 3 power-domains = <&prm_coreaon>; 4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; 5 clock-names = "fck"; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 9 reg-names = "ap", "la", "ia0"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ 13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */ 14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */ 15 dma-ranges; 16 17 segment@0 { /* 0x4a000000 */ 18 compatible = "simple-pm-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 22 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 23 <0x00001000 0x00001000 0x001000>, /* ap 2 */ 24 <0x00002000 0x00002000 0x002000>, /* ap 3 */ 25 <0x00004000 0x00004000 0x001000>, /* ap 4 */ 26 <0x00005000 0x00005000 0x001000>, /* ap 5 */ 27 <0x00006000 0x00006000 0x001000>, /* ap 6 */ 28 <0x00008000 0x00008000 0x002000>, /* ap 7 */ 29 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ 30 <0x00056000 0x00056000 0x001000>, /* ap 9 */ 31 <0x00057000 0x00057000 0x001000>, /* ap 10 */ 32 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ 33 <0x00060000 0x00060000 0x001000>, /* ap 12 */ 34 <0x00080000 0x00080000 0x008000>, /* ap 13 */ 35 <0x00088000 0x00088000 0x001000>, /* ap 14 */ 36 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ 37 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ 38 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ 39 <0x000da000 0x000da000 0x001000>, /* ap 18 */ 40 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ 41 <0x000de000 0x000de000 0x001000>, /* ap 20 */ 42 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ 43 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ 44 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ 45 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ 46 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ 47 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ 48 <0x00090000 0x00090000 0x008000>, /* ap 59 */ 49 <0x00098000 0x00098000 0x001000>; /* ap 60 */ 50 51 target-module@2000 { /* 0x4a002000, ap 3 08.0 */ 52 compatible = "ti,sysc-omap4", "ti,sysc"; 53 reg = <0x2000 0x4>; 54 reg-names = "rev"; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges = <0x0 0x2000 0x2000>; 58 59 scm: scm@0 { 60 compatible = "ti,dra7-scm-core", "simple-bus"; 61 reg = <0 0x2000>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges = <0 0 0x2000>; 65 66 scm_conf: scm_conf@0 { 67 compatible = "syscon", "simple-bus"; 68 reg = <0x0 0x1400>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0 0x0 0x1400>; 72 73 pbias_regulator: pbias_regulator@e00 { 74 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 75 reg = <0xe00 0x4>; 76 syscon = <&scm_conf>; 77 pbias_mmc_reg: pbias_mmc_omap5 { 78 regulator-name = "pbias_mmc_omap5"; 79 regulator-min-microvolt = <1800000>; 80 regulator-max-microvolt = <3300000>; 81 }; 82 }; 83 84 phy_gmii_sel: phy-gmii-sel { 85 compatible = "ti,dra7xx-phy-gmii-sel"; 86 reg = <0x554 0x4>; 87 #phy-cells = <1>; 88 }; 89 90 scm_conf_clocks: clocks { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 }; 94 }; 95 96 dra7_pmx_core: pinmux@1400 { 97 compatible = "ti,dra7-padconf", 98 "pinctrl-single"; 99 reg = <0x1400 0x0468>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 #pinctrl-cells = <1>; 103 #interrupt-cells = <1>; 104 interrupt-controller; 105 pinctrl-single,register-width = <32>; 106 pinctrl-single,function-mask = <0x3fffffff>; 107 }; 108 109 scm_conf1: scm_conf@1c04 { 110 compatible = "syscon"; 111 reg = <0x1c04 0x0020>; 112 #syscon-cells = <2>; 113 }; 114 115 scm_conf_pcie: scm_conf@1c24 { 116 compatible = "syscon"; 117 reg = <0x1c24 0x0024>; 118 }; 119 120 sdma_xbar: dma-router@b78 { 121 compatible = "ti,dra7-dma-crossbar"; 122 reg = <0xb78 0xfc>; 123 #dma-cells = <1>; 124 dma-requests = <205>; 125 ti,dma-safe-map = <0>; 126 dma-masters = <&sdma>; 127 }; 128 129 edma_xbar: dma-router@c78 { 130 compatible = "ti,dra7-dma-crossbar"; 131 reg = <0xc78 0x7c>; 132 #dma-cells = <2>; 133 dma-requests = <204>; 134 ti,dma-safe-map = <0>; 135 dma-masters = <&edma>; 136 }; 137 }; 138 }; 139 140 target-module@5000 { /* 0x4a005000, ap 5 10.0 */ 141 compatible = "ti,sysc-omap4", "ti,sysc"; 142 reg = <0x5000 0x4>; 143 reg-names = "rev"; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0x0 0x5000 0x1000>; 147 148 cm_core_aon: cm_core_aon@0 { 149 compatible = "ti,dra7-cm-core-aon", 150 "simple-bus"; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 reg = <0 0x2000>; 154 ranges = <0 0 0x2000>; 155 156 cm_core_aon_clocks: clocks { 157 #address-cells = <1>; 158 #size-cells = <0>; 159 }; 160 161 cm_core_aon_clockdomains: clockdomains { 162 }; 163 }; 164 }; 165 166 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ 167 compatible = "ti,sysc-omap4", "ti,sysc"; 168 reg = <0x8000 0x4>; 169 reg-names = "rev"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 ranges = <0x0 0x8000 0x2000>; 173 174 cm_core: cm_core@0 { 175 compatible = "ti,dra7-cm-core", "simple-bus"; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 reg = <0 0x3000>; 179 ranges = <0 0 0x3000>; 180 181 cm_core_clocks: clocks { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 }; 185 186 cm_core_clockdomains: clockdomains { 187 }; 188 }; 189 }; 190 191 target-module@56000 { /* 0x4a056000, ap 9 02.0 */ 192 compatible = "ti,sysc-omap2", "ti,sysc"; 193 reg = <0x56000 0x4>, 194 <0x5602c 0x4>, 195 <0x56028 0x4>; 196 reg-names = "rev", "sysc", "syss"; 197 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 198 SYSC_OMAP2_EMUFREE | 199 SYSC_OMAP2_SOFTRESET | 200 SYSC_OMAP2_AUTOIDLE)>; 201 ti,sysc-midle = <SYSC_IDLE_FORCE>, 202 <SYSC_IDLE_NO>, 203 <SYSC_IDLE_SMART>, 204 <SYSC_IDLE_SMART_WKUP>; 205 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 206 <SYSC_IDLE_NO>, 207 <SYSC_IDLE_SMART>, 208 <SYSC_IDLE_SMART_WKUP>; 209 ti,syss-mask = <1>; 210 /* Domains (P, C): core_pwrdm, dma_clkdm */ 211 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; 212 clock-names = "fck"; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 ranges = <0x0 0x56000 0x1000>; 216 217 sdma: dma-controller@0 { 218 compatible = "ti,omap4430-sdma", "ti,omap-sdma"; 219 reg = <0x0 0x1000>; 220 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 224 #dma-cells = <1>; 225 dma-channels = <32>; 226 dma-requests = <127>; 227 }; 228 }; 229 230 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ 231 compatible = "ti,sysc"; 232 status = "disabled"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges = <0x0 0x5e000 0x2000>; 236 }; 237 238 target-module@80000 { /* 0x4a080000, ap 13 20.0 */ 239 compatible = "ti,sysc-omap2", "ti,sysc"; 240 reg = <0x80000 0x4>, 241 <0x80010 0x4>, 242 <0x80014 0x4>; 243 reg-names = "rev", "sysc", "syss"; 244 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 245 SYSC_OMAP2_AUTOIDLE)>; 246 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 247 <SYSC_IDLE_NO>, 248 <SYSC_IDLE_SMART>; 249 ti,syss-mask = <1>; 250 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 251 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; 252 clock-names = "fck"; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 ranges = <0x0 0x80000 0x8000>; 256 257 ocp2scp@0 { 258 compatible = "ti,omap-ocp2scp"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 ranges = <0 0 0x8000>; 262 reg = <0x0 0x20>; 263 264 usb2_phy1: phy@4000 { 265 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 266 reg = <0x4000 0x400>; 267 syscon-phy-power = <&scm_conf 0x300>; 268 clocks = <&usb_phy1_always_on_clk32k>, 269 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; 270 clock-names = "wkupclk", 271 "refclk"; 272 #phy-cells = <0>; 273 }; 274 275 usb2_phy2: phy@5000 { 276 compatible = "ti,dra7x-usb2-phy2", 277 "ti,omap-usb2"; 278 reg = <0x5000 0x400>; 279 syscon-phy-power = <&scm_conf 0xe74>; 280 clocks = <&usb_phy2_always_on_clk32k>, 281 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; 282 clock-names = "wkupclk", 283 "refclk"; 284 #phy-cells = <0>; 285 }; 286 287 usb3_phy1: phy@4400 { 288 compatible = "ti,omap-usb3"; 289 reg = <0x4400 0x80>, 290 <0x4800 0x64>, 291 <0x4c00 0x40>; 292 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 293 syscon-phy-power = <&scm_conf 0x370>; 294 clocks = <&usb_phy3_always_on_clk32k>, 295 <&sys_clkin1>, 296 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; 297 clock-names = "wkupclk", 298 "sysclk", 299 "refclk"; 300 #phy-cells = <0>; 301 }; 302 }; 303 }; 304 305 target-module@90000 { /* 0x4a090000, ap 59 42.0 */ 306 compatible = "ti,sysc-omap2", "ti,sysc"; 307 reg = <0x90000 0x4>, 308 <0x90010 0x4>, 309 <0x90014 0x4>; 310 reg-names = "rev", "sysc", "syss"; 311 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 312 SYSC_OMAP2_AUTOIDLE)>; 313 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 314 <SYSC_IDLE_NO>, 315 <SYSC_IDLE_SMART>; 316 ti,syss-mask = <1>; 317 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 318 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; 319 clock-names = "fck"; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges = <0x0 0x90000 0x8000>; 323 324 ocp2scp@0 { 325 compatible = "ti,omap-ocp2scp"; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 ranges = <0 0 0x8000>; 329 reg = <0x0 0x20>; 330 331 pcie1_phy: pciephy@4000 { 332 compatible = "ti,phy-pipe3-pcie"; 333 reg = <0x4000 0x80>, /* phy_rx */ 334 <0x4400 0x64>; /* phy_tx */ 335 reg-names = "phy_rx", "phy_tx"; 336 syscon-phy-power = <&scm_conf_pcie 0x1c>; 337 syscon-pcs = <&scm_conf_pcie 0x10>; 338 clocks = <&dpll_pcie_ref_ck>, 339 <&dpll_pcie_ref_m2ldo_ck>, 340 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, 341 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, 342 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, 343 <&optfclk_pciephy_div>, 344 <&sys_clkin1>; 345 clock-names = "dpll_ref", "dpll_ref_m2", 346 "wkupclk", "refclk", 347 "div-clk", "phy-div", "sysclk"; 348 #phy-cells = <0>; 349 }; 350 351 pcie2_phy: pciephy@5000 { 352 compatible = "ti,phy-pipe3-pcie"; 353 reg = <0x5000 0x80>, /* phy_rx */ 354 <0x5400 0x64>; /* phy_tx */ 355 reg-names = "phy_rx", "phy_tx"; 356 syscon-phy-power = <&scm_conf_pcie 0x20>; 357 syscon-pcs = <&scm_conf_pcie 0x10>; 358 clocks = <&dpll_pcie_ref_ck>, 359 <&dpll_pcie_ref_m2ldo_ck>, 360 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, 361 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, 362 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, 363 <&optfclk_pciephy_div>, 364 <&sys_clkin1>; 365 clock-names = "dpll_ref", "dpll_ref_m2", 366 "wkupclk", "refclk", 367 "div-clk", "phy-div", "sysclk"; 368 #phy-cells = <0>; 369 status = "disabled"; 370 }; 371 372 sata_phy: phy@6000 { 373 compatible = "ti,phy-pipe3-sata"; 374 reg = <0x6000 0x80>, /* phy_rx */ 375 <0x6400 0x64>, /* phy_tx */ 376 <0x6800 0x40>; /* pll_ctrl */ 377 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 378 syscon-phy-power = <&scm_conf 0x374>; 379 clocks = <&sys_clkin1>, 380 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; 381 clock-names = "sysclk", "refclk"; 382 syscon-pllreset = <&scm_conf 0x3fc>; 383 #phy-cells = <0>; 384 }; 385 }; 386 }; 387 388 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ 389 compatible = "ti,sysc"; 390 status = "disabled"; 391 #address-cells = <1>; 392 #size-cells = <1>; 393 ranges = <0x0 0xa0000 0x8000>; 394 }; 395 396 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ 397 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 398 reg = <0xd9038 0x4>; 399 reg-names = "sysc"; 400 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 401 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 402 <SYSC_IDLE_NO>, 403 <SYSC_IDLE_SMART>, 404 <SYSC_IDLE_SMART_WKUP>; 405 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 406 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; 407 clock-names = "fck"; 408 #address-cells = <1>; 409 #size-cells = <1>; 410 ranges = <0x0 0xd9000 0x1000>; 411 412 /* SmartReflex child device marked reserved in TRM */ 413 }; 414 415 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ 416 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 417 reg = <0xdd038 0x4>; 418 reg-names = "sysc"; 419 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 420 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 421 <SYSC_IDLE_NO>, 422 <SYSC_IDLE_SMART>, 423 <SYSC_IDLE_SMART_WKUP>; 424 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 425 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; 426 clock-names = "fck"; 427 #address-cells = <1>; 428 #size-cells = <1>; 429 ranges = <0x0 0xdd000 0x1000>; 430 431 /* SmartReflex child device marked reserved in TRM */ 432 }; 433 434 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ 435 compatible = "ti,sysc"; 436 status = "disabled"; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges = <0x0 0xe0000 0x1000>; 440 }; 441 442 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ 443 compatible = "ti,sysc-omap4", "ti,sysc"; 444 reg = <0xf4000 0x4>, 445 <0xf4010 0x4>; 446 reg-names = "rev", "sysc"; 447 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 448 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 449 <SYSC_IDLE_NO>, 450 <SYSC_IDLE_SMART>; 451 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 452 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; 453 clock-names = "fck"; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 ranges = <0x0 0xf4000 0x1000>; 457 458 mailbox1: mailbox@0 { 459 compatible = "ti,omap4-mailbox"; 460 reg = <0x0 0x200>; 461 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 464 #mbox-cells = <1>; 465 ti,mbox-num-users = <3>; 466 ti,mbox-num-fifos = <8>; 467 status = "disabled"; 468 }; 469 }; 470 471 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ 472 compatible = "ti,sysc-omap2", "ti,sysc"; 473 reg = <0xf6000 0x4>, 474 <0xf6010 0x4>, 475 <0xf6014 0x4>; 476 reg-names = "rev", "sysc", "syss"; 477 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 478 SYSC_OMAP2_SOFTRESET | 479 SYSC_OMAP2_AUTOIDLE)>; 480 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 481 <SYSC_IDLE_NO>, 482 <SYSC_IDLE_SMART>; 483 ti,syss-mask = <1>; 484 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 485 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; 486 clock-names = "fck"; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 ranges = <0x0 0xf6000 0x1000>; 490 491 hwspinlock: spinlock@0 { 492 compatible = "ti,omap4-hwspinlock"; 493 reg = <0x0 0x1000>; 494 #hwlock-cells = <1>; 495 }; 496 }; 497 }; 498 499 segment@100000 { /* 0x4a100000 */ 500 compatible = "simple-pm-bus"; 501 #address-cells = <1>; 502 #size-cells = <1>; 503 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ 504 <0x00003000 0x00103000 0x001000>, /* ap 28 */ 505 <0x00008000 0x00108000 0x001000>, /* ap 29 */ 506 <0x00009000 0x00109000 0x001000>, /* ap 30 */ 507 <0x00040000 0x00140000 0x010000>, /* ap 31 */ 508 <0x00050000 0x00150000 0x001000>, /* ap 32 */ 509 <0x00051000 0x00151000 0x001000>, /* ap 33 */ 510 <0x00052000 0x00152000 0x001000>, /* ap 34 */ 511 <0x00053000 0x00153000 0x001000>, /* ap 35 */ 512 <0x00054000 0x00154000 0x001000>, /* ap 36 */ 513 <0x00055000 0x00155000 0x001000>, /* ap 37 */ 514 <0x00056000 0x00156000 0x001000>, /* ap 38 */ 515 <0x00057000 0x00157000 0x001000>, /* ap 39 */ 516 <0x00058000 0x00158000 0x001000>, /* ap 40 */ 517 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ 518 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ 519 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ 520 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ 521 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ 522 <0x00060000 0x00160000 0x001000>, /* ap 48 */ 523 <0x00061000 0x00161000 0x001000>, /* ap 49 */ 524 <0x00062000 0x00162000 0x001000>, /* ap 50 */ 525 <0x00063000 0x00163000 0x001000>, /* ap 51 */ 526 <0x00064000 0x00164000 0x001000>, /* ap 52 */ 527 <0x00065000 0x00165000 0x001000>, /* ap 53 */ 528 <0x00066000 0x00166000 0x001000>, /* ap 54 */ 529 <0x00067000 0x00167000 0x001000>, /* ap 55 */ 530 <0x00068000 0x00168000 0x001000>, /* ap 56 */ 531 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ 532 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ 533 <0x00071000 0x00171000 0x001000>, /* ap 61 */ 534 <0x00072000 0x00172000 0x001000>, /* ap 62 */ 535 <0x00073000 0x00173000 0x001000>, /* ap 63 */ 536 <0x00074000 0x00174000 0x001000>, /* ap 64 */ 537 <0x00075000 0x00175000 0x001000>, /* ap 65 */ 538 <0x00076000 0x00176000 0x001000>, /* ap 66 */ 539 <0x00077000 0x00177000 0x001000>, /* ap 67 */ 540 <0x00078000 0x00178000 0x001000>, /* ap 68 */ 541 <0x00081000 0x00181000 0x001000>, /* ap 69 */ 542 <0x00082000 0x00182000 0x001000>, /* ap 70 */ 543 <0x00083000 0x00183000 0x001000>, /* ap 71 */ 544 <0x00084000 0x00184000 0x001000>, /* ap 72 */ 545 <0x00085000 0x00185000 0x001000>, /* ap 73 */ 546 <0x00086000 0x00186000 0x001000>, /* ap 74 */ 547 <0x00087000 0x00187000 0x001000>, /* ap 75 */ 548 <0x00088000 0x00188000 0x001000>, /* ap 76 */ 549 <0x00069000 0x00169000 0x001000>, /* ap 103 */ 550 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ 551 <0x00079000 0x00179000 0x001000>, /* ap 105 */ 552 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ 553 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ 554 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ 555 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ 556 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ 557 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ 558 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ 559 <0x00059000 0x00159000 0x001000>, /* ap 125 */ 560 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ 561 dma-ranges; 562 563 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ 564 compatible = "ti,sysc"; 565 status = "disabled"; 566 #address-cells = <1>; 567 #size-cells = <1>; 568 ranges = <0x0 0x2000 0x1000>; 569 }; 570 571 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ 572 compatible = "ti,sysc"; 573 status = "disabled"; 574 #address-cells = <1>; 575 #size-cells = <1>; 576 ranges = <0x0 0x8000 0x1000>; 577 }; 578 579 target-module@40000 { /* 0x4a140000, ap 31 06.0 */ 580 compatible = "ti,sysc-omap4", "ti,sysc"; 581 reg = <0x400fc 4>, 582 <0x41100 4>; 583 reg-names = "rev", "sysc"; 584 ti,sysc-midle = <SYSC_IDLE_FORCE>, 585 <SYSC_IDLE_NO>, 586 <SYSC_IDLE_SMART>; 587 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 588 <SYSC_IDLE_NO>, 589 <SYSC_IDLE_SMART>, 590 <SYSC_IDLE_SMART_WKUP>; 591 power-domains = <&prm_l3init>; 592 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>; 593 clock-names = "fck"; 594 #size-cells = <1>; 595 #address-cells = <1>; 596 ranges = <0x0 0x40000 0x10000>; 597 598 sata: sata@0 { 599 compatible = "snps,dwc-ahci"; 600 reg = <0 0x1100>, <0x1100 0x8>; 601 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 602 phys = <&sata_phy>; 603 phy-names = "sata-phy"; 604 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; 605 ports-implemented = <0x1>; 606 }; 607 }; 608 609 target-module@51000 { /* 0x4a151000, ap 33 50.0 */ 610 compatible = "ti,sysc"; 611 status = "disabled"; 612 #address-cells = <1>; 613 #size-cells = <1>; 614 ranges = <0x0 0x51000 0x1000>; 615 }; 616 617 target-module@53000 { /* 0x4a153000, ap 35 54.0 */ 618 compatible = "ti,sysc"; 619 status = "disabled"; 620 #address-cells = <1>; 621 #size-cells = <1>; 622 ranges = <0x0 0x53000 0x1000>; 623 }; 624 625 target-module@55000 { /* 0x4a155000, ap 37 46.0 */ 626 compatible = "ti,sysc"; 627 status = "disabled"; 628 #address-cells = <1>; 629 #size-cells = <1>; 630 ranges = <0x0 0x55000 0x1000>; 631 }; 632 633 target-module@57000 { /* 0x4a157000, ap 39 58.0 */ 634 compatible = "ti,sysc"; 635 status = "disabled"; 636 #address-cells = <1>; 637 #size-cells = <1>; 638 ranges = <0x0 0x57000 0x1000>; 639 }; 640 641 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ 642 compatible = "ti,sysc"; 643 status = "disabled"; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 ranges = <0x0 0x59000 0x1000>; 647 }; 648 649 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ 650 compatible = "ti,sysc"; 651 status = "disabled"; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 ranges = <0x0 0x5b000 0x1000>; 655 }; 656 657 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ 658 compatible = "ti,sysc"; 659 status = "disabled"; 660 #address-cells = <1>; 661 #size-cells = <1>; 662 ranges = <0x0 0x5d000 0x1000>; 663 }; 664 665 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ 666 compatible = "ti,sysc"; 667 status = "disabled"; 668 #address-cells = <1>; 669 #size-cells = <1>; 670 ranges = <0x0 0x5f000 0x1000>; 671 }; 672 673 target-module@61000 { /* 0x4a161000, ap 49 32.0 */ 674 compatible = "ti,sysc"; 675 status = "disabled"; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges = <0x0 0x61000 0x1000>; 679 }; 680 681 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ 682 compatible = "ti,sysc"; 683 status = "disabled"; 684 #address-cells = <1>; 685 #size-cells = <1>; 686 ranges = <0x0 0x63000 0x1000>; 687 }; 688 689 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ 690 compatible = "ti,sysc"; 691 status = "disabled"; 692 #address-cells = <1>; 693 #size-cells = <1>; 694 ranges = <0x0 0x65000 0x1000>; 695 }; 696 697 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ 698 compatible = "ti,sysc"; 699 status = "disabled"; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 ranges = <0x0 0x67000 0x1000>; 703 }; 704 705 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ 706 compatible = "ti,sysc"; 707 status = "disabled"; 708 #address-cells = <1>; 709 #size-cells = <1>; 710 ranges = <0x0 0x69000 0x1000>; 711 }; 712 713 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ 714 compatible = "ti,sysc"; 715 status = "disabled"; 716 #address-cells = <1>; 717 #size-cells = <1>; 718 ranges = <0x0 0x6b000 0x1000>; 719 }; 720 721 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ 722 compatible = "ti,sysc"; 723 status = "disabled"; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 ranges = <0x0 0x6d000 0x1000>; 727 }; 728 729 target-module@71000 { /* 0x4a171000, ap 61 48.0 */ 730 compatible = "ti,sysc"; 731 status = "disabled"; 732 #address-cells = <1>; 733 #size-cells = <1>; 734 ranges = <0x0 0x71000 0x1000>; 735 }; 736 737 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ 738 compatible = "ti,sysc"; 739 status = "disabled"; 740 #address-cells = <1>; 741 #size-cells = <1>; 742 ranges = <0x0 0x73000 0x1000>; 743 }; 744 745 target-module@75000 { /* 0x4a175000, ap 65 64.0 */ 746 compatible = "ti,sysc"; 747 status = "disabled"; 748 #address-cells = <1>; 749 #size-cells = <1>; 750 ranges = <0x0 0x75000 0x1000>; 751 }; 752 753 target-module@77000 { /* 0x4a177000, ap 67 66.0 */ 754 compatible = "ti,sysc"; 755 status = "disabled"; 756 #address-cells = <1>; 757 #size-cells = <1>; 758 ranges = <0x0 0x77000 0x1000>; 759 }; 760 761 target-module@79000 { /* 0x4a179000, ap 105 34.0 */ 762 compatible = "ti,sysc"; 763 status = "disabled"; 764 #address-cells = <1>; 765 #size-cells = <1>; 766 ranges = <0x0 0x79000 0x1000>; 767 }; 768 769 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ 770 compatible = "ti,sysc"; 771 status = "disabled"; 772 #address-cells = <1>; 773 #size-cells = <1>; 774 ranges = <0x0 0x7b000 0x1000>; 775 }; 776 777 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ 778 compatible = "ti,sysc"; 779 status = "disabled"; 780 #address-cells = <1>; 781 #size-cells = <1>; 782 ranges = <0x0 0x7d000 0x1000>; 783 }; 784 785 target-module@81000 { /* 0x4a181000, ap 69 26.0 */ 786 compatible = "ti,sysc"; 787 status = "disabled"; 788 #address-cells = <1>; 789 #size-cells = <1>; 790 ranges = <0x0 0x81000 0x1000>; 791 }; 792 793 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ 794 compatible = "ti,sysc"; 795 status = "disabled"; 796 #address-cells = <1>; 797 #size-cells = <1>; 798 ranges = <0x0 0x83000 0x1000>; 799 }; 800 801 target-module@85000 { /* 0x4a185000, ap 73 36.0 */ 802 compatible = "ti,sysc"; 803 status = "disabled"; 804 #address-cells = <1>; 805 #size-cells = <1>; 806 ranges = <0x0 0x85000 0x1000>; 807 }; 808 809 target-module@87000 { /* 0x4a187000, ap 75 74.0 */ 810 compatible = "ti,sysc"; 811 status = "disabled"; 812 #address-cells = <1>; 813 #size-cells = <1>; 814 ranges = <0x0 0x87000 0x1000>; 815 }; 816 }; 817 818 segment@200000 { /* 0x4a200000 */ 819 compatible = "simple-pm-bus"; 820 #address-cells = <1>; 821 #size-cells = <1>; 822 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ 823 <0x00019000 0x00219000 0x001000>, /* ap 44 */ 824 <0x00000000 0x00200000 0x001000>, /* ap 77 */ 825 <0x00001000 0x00201000 0x001000>, /* ap 78 */ 826 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ 827 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ 828 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ 829 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ 830 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ 831 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ 832 <0x00010000 0x00210000 0x001000>, /* ap 85 */ 833 <0x00011000 0x00211000 0x001000>, /* ap 86 */ 834 <0x00012000 0x00212000 0x001000>, /* ap 87 */ 835 <0x00013000 0x00213000 0x001000>, /* ap 88 */ 836 <0x00014000 0x00214000 0x001000>, /* ap 89 */ 837 <0x00015000 0x00215000 0x001000>, /* ap 90 */ 838 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ 839 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ 840 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ 841 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ 842 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ 843 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ 844 <0x00020000 0x00220000 0x001000>, /* ap 97 */ 845 <0x00021000 0x00221000 0x001000>, /* ap 98 */ 846 <0x00024000 0x00224000 0x001000>, /* ap 99 */ 847 <0x00025000 0x00225000 0x001000>, /* ap 100 */ 848 <0x00026000 0x00226000 0x001000>, /* ap 101 */ 849 <0x00027000 0x00227000 0x001000>, /* ap 102 */ 850 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ 851 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ 852 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ 853 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ 854 <0x00030000 0x00230000 0x001000>, /* ap 113 */ 855 <0x00031000 0x00231000 0x001000>, /* ap 114 */ 856 <0x00032000 0x00232000 0x001000>, /* ap 115 */ 857 <0x00033000 0x00233000 0x001000>, /* ap 116 */ 858 <0x00034000 0x00234000 0x001000>, /* ap 117 */ 859 <0x00035000 0x00235000 0x001000>, /* ap 118 */ 860 <0x00036000 0x00236000 0x001000>, /* ap 119 */ 861 <0x00037000 0x00237000 0x001000>, /* ap 120 */ 862 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ 863 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ 864 865 target-module@0 { /* 0x4a200000, ap 77 3e.0 */ 866 compatible = "ti,sysc"; 867 status = "disabled"; 868 #address-cells = <1>; 869 #size-cells = <1>; 870 ranges = <0x0 0x0 0x1000>; 871 }; 872 873 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ 874 compatible = "ti,sysc"; 875 status = "disabled"; 876 #address-cells = <1>; 877 #size-cells = <1>; 878 ranges = <0x0 0xa000 0x1000>; 879 }; 880 881 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ 882 compatible = "ti,sysc"; 883 status = "disabled"; 884 #address-cells = <1>; 885 #size-cells = <1>; 886 ranges = <0x0 0xc000 0x1000>; 887 }; 888 889 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ 890 compatible = "ti,sysc"; 891 status = "disabled"; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 ranges = <0x0 0xe000 0x1000>; 895 }; 896 897 target-module@10000 { /* 0x4a210000, ap 85 14.0 */ 898 compatible = "ti,sysc"; 899 status = "disabled"; 900 #address-cells = <1>; 901 #size-cells = <1>; 902 ranges = <0x0 0x10000 0x1000>; 903 }; 904 905 target-module@12000 { /* 0x4a212000, ap 87 16.0 */ 906 compatible = "ti,sysc"; 907 status = "disabled"; 908 #address-cells = <1>; 909 #size-cells = <1>; 910 ranges = <0x0 0x12000 0x1000>; 911 }; 912 913 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ 914 compatible = "ti,sysc"; 915 status = "disabled"; 916 #address-cells = <1>; 917 #size-cells = <1>; 918 ranges = <0x0 0x14000 0x1000>; 919 }; 920 921 target-module@18000 { /* 0x4a218000, ap 43 12.0 */ 922 compatible = "ti,sysc"; 923 status = "disabled"; 924 #address-cells = <1>; 925 #size-cells = <1>; 926 ranges = <0x0 0x18000 0x1000>; 927 }; 928 929 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ 930 compatible = "ti,sysc"; 931 status = "disabled"; 932 #address-cells = <1>; 933 #size-cells = <1>; 934 ranges = <0x0 0x1a000 0x1000>; 935 }; 936 937 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ 938 compatible = "ti,sysc"; 939 status = "disabled"; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 ranges = <0x0 0x1c000 0x1000>; 943 }; 944 945 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ 946 compatible = "ti,sysc"; 947 status = "disabled"; 948 #address-cells = <1>; 949 #size-cells = <1>; 950 ranges = <0x0 0x1e000 0x1000>; 951 }; 952 953 target-module@20000 { /* 0x4a220000, ap 97 24.0 */ 954 compatible = "ti,sysc"; 955 status = "disabled"; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 ranges = <0x0 0x20000 0x1000>; 959 }; 960 961 target-module@24000 { /* 0x4a224000, ap 99 44.0 */ 962 compatible = "ti,sysc"; 963 status = "disabled"; 964 #address-cells = <1>; 965 #size-cells = <1>; 966 ranges = <0x0 0x24000 0x1000>; 967 }; 968 969 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ 970 compatible = "ti,sysc"; 971 status = "disabled"; 972 #address-cells = <1>; 973 #size-cells = <1>; 974 ranges = <0x0 0x26000 0x1000>; 975 }; 976 977 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ 978 compatible = "ti,sysc"; 979 status = "disabled"; 980 #address-cells = <1>; 981 #size-cells = <1>; 982 ranges = <0x0 0x2a000 0x1000>; 983 }; 984 985 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ 986 compatible = "ti,sysc"; 987 status = "disabled"; 988 #address-cells = <1>; 989 #size-cells = <1>; 990 ranges = <0x0 0x2c000 0x1000>; 991 }; 992 993 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ 994 compatible = "ti,sysc"; 995 status = "disabled"; 996 #address-cells = <1>; 997 #size-cells = <1>; 998 ranges = <0x0 0x2e000 0x1000>; 999 }; 1000 1001 target-module@30000 { /* 0x4a230000, ap 113 70.0 */ 1002 compatible = "ti,sysc"; 1003 status = "disabled"; 1004 #address-cells = <1>; 1005 #size-cells = <1>; 1006 ranges = <0x0 0x30000 0x1000>; 1007 }; 1008 1009 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ 1010 compatible = "ti,sysc"; 1011 status = "disabled"; 1012 #address-cells = <1>; 1013 #size-cells = <1>; 1014 ranges = <0x0 0x32000 0x1000>; 1015 }; 1016 1017 target-module@34000 { /* 0x4a234000, ap 117 76.1 */ 1018 compatible = "ti,sysc"; 1019 status = "disabled"; 1020 #address-cells = <1>; 1021 #size-cells = <1>; 1022 ranges = <0x0 0x34000 0x1000>; 1023 }; 1024 1025 target-module@36000 { /* 0x4a236000, ap 119 62.0 */ 1026 compatible = "ti,sysc"; 1027 status = "disabled"; 1028 #address-cells = <1>; 1029 #size-cells = <1>; 1030 ranges = <0x0 0x36000 0x1000>; 1031 }; 1032 }; 1033}; 1034 1035&l4_per1 { /* 0x48000000 */ 1036 compatible = "ti,dra7-l4-per1", "simple-pm-bus"; 1037 power-domains = <&prm_l4per>; 1038 clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>; 1039 clock-names = "fck"; 1040 reg = <0x48000000 0x800>, 1041 <0x48000800 0x800>, 1042 <0x48001000 0x400>, 1043 <0x48001400 0x400>, 1044 <0x48001800 0x400>, 1045 <0x48001c00 0x400>; 1046 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 1047 #address-cells = <1>; 1048 #size-cells = <1>; 1049 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ 1050 <0x00200000 0x48200000 0x200000>; /* segment 1 */ 1051 1052 segment@0 { /* 0x48000000 */ 1053 compatible = "simple-pm-bus"; 1054 #address-cells = <1>; 1055 #size-cells = <1>; 1056 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1057 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 1058 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 1059 <0x00020000 0x00020000 0x001000>, /* ap 3 */ 1060 <0x00021000 0x00021000 0x001000>, /* ap 4 */ 1061 <0x00032000 0x00032000 0x001000>, /* ap 5 */ 1062 <0x00033000 0x00033000 0x001000>, /* ap 6 */ 1063 <0x00034000 0x00034000 0x001000>, /* ap 7 */ 1064 <0x00035000 0x00035000 0x001000>, /* ap 8 */ 1065 <0x00036000 0x00036000 0x001000>, /* ap 9 */ 1066 <0x00037000 0x00037000 0x001000>, /* ap 10 */ 1067 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ 1068 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ 1069 <0x00055000 0x00055000 0x001000>, /* ap 13 */ 1070 <0x00056000 0x00056000 0x001000>, /* ap 14 */ 1071 <0x00057000 0x00057000 0x001000>, /* ap 15 */ 1072 <0x00058000 0x00058000 0x001000>, /* ap 16 */ 1073 <0x00059000 0x00059000 0x001000>, /* ap 17 */ 1074 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ 1075 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ 1076 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ 1077 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ 1078 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ 1079 <0x00060000 0x00060000 0x001000>, /* ap 23 */ 1080 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ 1081 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ 1082 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ 1083 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ 1084 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ 1085 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ 1086 <0x00070000 0x00070000 0x001000>, /* ap 30 */ 1087 <0x00071000 0x00071000 0x001000>, /* ap 31 */ 1088 <0x00072000 0x00072000 0x001000>, /* ap 32 */ 1089 <0x00073000 0x00073000 0x001000>, /* ap 33 */ 1090 <0x00061000 0x00061000 0x001000>, /* ap 34 */ 1091 <0x00053000 0x00053000 0x001000>, /* ap 35 */ 1092 <0x00054000 0x00054000 0x001000>, /* ap 36 */ 1093 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ 1094 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ 1095 <0x00078000 0x00078000 0x001000>, /* ap 39 */ 1096 <0x00079000 0x00079000 0x001000>, /* ap 40 */ 1097 <0x00086000 0x00086000 0x001000>, /* ap 41 */ 1098 <0x00087000 0x00087000 0x001000>, /* ap 42 */ 1099 <0x00088000 0x00088000 0x001000>, /* ap 43 */ 1100 <0x00089000 0x00089000 0x001000>, /* ap 44 */ 1101 <0x00051000 0x00051000 0x001000>, /* ap 45 */ 1102 <0x00052000 0x00052000 0x001000>, /* ap 46 */ 1103 <0x00098000 0x00098000 0x001000>, /* ap 47 */ 1104 <0x00099000 0x00099000 0x001000>, /* ap 48 */ 1105 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ 1106 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ 1107 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ 1108 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ 1109 <0x00068000 0x00068000 0x001000>, /* ap 53 */ 1110 <0x00069000 0x00069000 0x001000>, /* ap 54 */ 1111 <0x00090000 0x00090000 0x002000>, /* ap 55 */ 1112 <0x00092000 0x00092000 0x001000>, /* ap 56 */ 1113 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ 1114 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ 1115 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ 1116 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ 1117 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ 1118 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ 1119 <0x00066000 0x00066000 0x001000>, /* ap 63 */ 1120 <0x00067000 0x00067000 0x001000>, /* ap 64 */ 1121 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ 1122 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ 1123 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ 1124 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ 1125 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ 1126 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ 1127 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ 1128 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ 1129 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ 1130 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ 1131 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ 1132 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ 1133 <0x00001400 0x00001400 0x000400>, /* ap 77 */ 1134 <0x00001800 0x00001800 0x000400>, /* ap 78 */ 1135 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ 1136 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ 1137 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ 1138 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ 1139 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ 1140 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ 1141 1142 target-module@20000 { /* 0x48020000, ap 3 04.0 */ 1143 compatible = "ti,sysc-omap2", "ti,sysc"; 1144 reg = <0x20050 0x4>, 1145 <0x20054 0x4>, 1146 <0x20058 0x4>; 1147 reg-names = "rev", "sysc", "syss"; 1148 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1149 SYSC_OMAP2_SOFTRESET | 1150 SYSC_OMAP2_AUTOIDLE)>; 1151 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1152 <SYSC_IDLE_NO>, 1153 <SYSC_IDLE_SMART>, 1154 <SYSC_IDLE_SMART_WKUP>; 1155 ti,syss-mask = <1>; 1156 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1157 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; 1158 clock-names = "fck"; 1159 #address-cells = <1>; 1160 #size-cells = <1>; 1161 ranges = <0x0 0x20000 0x1000>; 1162 1163 uart3: serial@0 { 1164 compatible = "ti,dra742-uart"; 1165 reg = <0x0 0x100>; 1166 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1167 clock-frequency = <48000000>; 1168 status = "disabled"; 1169 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 1170 dma-names = "tx", "rx"; 1171 }; 1172 }; 1173 1174 target-module@32000 { /* 0x48032000, ap 5 3e.0 */ 1175 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1176 reg = <0x32000 0x4>, 1177 <0x32010 0x4>; 1178 reg-names = "rev", "sysc"; 1179 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1180 SYSC_OMAP4_SOFTRESET)>; 1181 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1182 <SYSC_IDLE_NO>, 1183 <SYSC_IDLE_SMART>, 1184 <SYSC_IDLE_SMART_WKUP>; 1185 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1186 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; 1187 clock-names = "fck"; 1188 #address-cells = <1>; 1189 #size-cells = <1>; 1190 ranges = <0x0 0x32000 0x1000>; 1191 1192 timer2: timer@0 { 1193 compatible = "ti,omap5430-timer"; 1194 reg = <0x0 0x80>; 1195 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>; 1196 clock-names = "fck", "timer_sys_ck"; 1197 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1198 }; 1199 }; 1200 1201 timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */ 1202 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1203 reg = <0x34000 0x4>, 1204 <0x34010 0x4>; 1205 reg-names = "rev", "sysc"; 1206 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1207 SYSC_OMAP4_SOFTRESET)>; 1208 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1209 <SYSC_IDLE_NO>, 1210 <SYSC_IDLE_SMART>, 1211 <SYSC_IDLE_SMART_WKUP>; 1212 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1213 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; 1214 clock-names = "fck"; 1215 #address-cells = <1>; 1216 #size-cells = <1>; 1217 ranges = <0x0 0x34000 0x1000>; 1218 1219 timer3: timer@0 { 1220 compatible = "ti,omap5430-timer"; 1221 reg = <0x0 0x80>; 1222 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>; 1223 clock-names = "fck", "timer_sys_ck"; 1224 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1225 }; 1226 }; 1227 1228 timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */ 1229 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1230 reg = <0x36000 0x4>, 1231 <0x36010 0x4>; 1232 reg-names = "rev", "sysc"; 1233 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1234 SYSC_OMAP4_SOFTRESET)>; 1235 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1236 <SYSC_IDLE_NO>, 1237 <SYSC_IDLE_SMART>, 1238 <SYSC_IDLE_SMART_WKUP>; 1239 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1240 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; 1241 clock-names = "fck"; 1242 #address-cells = <1>; 1243 #size-cells = <1>; 1244 ranges = <0x0 0x36000 0x1000>; 1245 1246 timer4: timer@0 { 1247 compatible = "ti,omap5430-timer"; 1248 reg = <0x0 0x80>; 1249 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>; 1250 clock-names = "fck", "timer_sys_ck"; 1251 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1252 }; 1253 }; 1254 1255 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ 1256 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1257 reg = <0x3e000 0x4>, 1258 <0x3e010 0x4>; 1259 reg-names = "rev", "sysc"; 1260 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1261 SYSC_OMAP4_SOFTRESET)>; 1262 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1263 <SYSC_IDLE_NO>, 1264 <SYSC_IDLE_SMART>, 1265 <SYSC_IDLE_SMART_WKUP>; 1266 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1267 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; 1268 clock-names = "fck"; 1269 #address-cells = <1>; 1270 #size-cells = <1>; 1271 ranges = <0x0 0x3e000 0x1000>; 1272 1273 timer9: timer@0 { 1274 compatible = "ti,omap5430-timer"; 1275 reg = <0x0 0x80>; 1276 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>; 1277 clock-names = "fck", "timer_sys_ck"; 1278 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1279 }; 1280 }; 1281 1282 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ 1283 compatible = "ti,sysc-omap2", "ti,sysc"; 1284 reg = <0x51000 0x4>, 1285 <0x51010 0x4>, 1286 <0x51114 0x4>; 1287 reg-names = "rev", "sysc", "syss"; 1288 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1289 SYSC_OMAP2_SOFTRESET | 1290 SYSC_OMAP2_AUTOIDLE)>; 1291 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1292 <SYSC_IDLE_NO>, 1293 <SYSC_IDLE_SMART>, 1294 <SYSC_IDLE_SMART_WKUP>; 1295 ti,syss-mask = <1>; 1296 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1297 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, 1298 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; 1299 clock-names = "fck", "dbclk"; 1300 #address-cells = <1>; 1301 #size-cells = <1>; 1302 ranges = <0x0 0x51000 0x1000>; 1303 1304 gpio7: gpio@0 { 1305 compatible = "ti,omap4-gpio"; 1306 reg = <0x0 0x200>; 1307 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1308 gpio-controller; 1309 #gpio-cells = <2>; 1310 interrupt-controller; 1311 #interrupt-cells = <2>; 1312 }; 1313 }; 1314 1315 target-module@53000 { /* 0x48053000, ap 35 36.0 */ 1316 compatible = "ti,sysc-omap2", "ti,sysc"; 1317 reg = <0x53000 0x4>, 1318 <0x53010 0x4>, 1319 <0x53114 0x4>; 1320 reg-names = "rev", "sysc", "syss"; 1321 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1322 SYSC_OMAP2_SOFTRESET | 1323 SYSC_OMAP2_AUTOIDLE)>; 1324 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1325 <SYSC_IDLE_NO>, 1326 <SYSC_IDLE_SMART>, 1327 <SYSC_IDLE_SMART_WKUP>; 1328 ti,syss-mask = <1>; 1329 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1330 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, 1331 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; 1332 clock-names = "fck", "dbclk"; 1333 #address-cells = <1>; 1334 #size-cells = <1>; 1335 ranges = <0x0 0x53000 0x1000>; 1336 1337 gpio8: gpio@0 { 1338 compatible = "ti,omap4-gpio"; 1339 reg = <0x0 0x200>; 1340 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1341 gpio-controller; 1342 #gpio-cells = <2>; 1343 interrupt-controller; 1344 #interrupt-cells = <2>; 1345 }; 1346 }; 1347 1348 gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ 1349 compatible = "ti,sysc-omap2", "ti,sysc"; 1350 reg = <0x55000 0x4>, 1351 <0x55010 0x4>, 1352 <0x55114 0x4>; 1353 reg-names = "rev", "sysc", "syss"; 1354 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1355 SYSC_OMAP2_SOFTRESET | 1356 SYSC_OMAP2_AUTOIDLE)>; 1357 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1358 <SYSC_IDLE_NO>, 1359 <SYSC_IDLE_SMART>, 1360 <SYSC_IDLE_SMART_WKUP>; 1361 ti,syss-mask = <1>; 1362 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1363 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, 1364 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; 1365 clock-names = "fck", "dbclk"; 1366 #address-cells = <1>; 1367 #size-cells = <1>; 1368 ranges = <0x0 0x55000 0x1000>; 1369 1370 gpio2: gpio@0 { 1371 compatible = "ti,omap4-gpio"; 1372 reg = <0x0 0x200>; 1373 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1374 gpio-controller; 1375 #gpio-cells = <2>; 1376 interrupt-controller; 1377 #interrupt-cells = <2>; 1378 }; 1379 }; 1380 1381 gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ 1382 compatible = "ti,sysc-omap2", "ti,sysc"; 1383 reg = <0x57000 0x4>, 1384 <0x57010 0x4>, 1385 <0x57114 0x4>; 1386 reg-names = "rev", "sysc", "syss"; 1387 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1388 SYSC_OMAP2_SOFTRESET | 1389 SYSC_OMAP2_AUTOIDLE)>; 1390 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1391 <SYSC_IDLE_NO>, 1392 <SYSC_IDLE_SMART>, 1393 <SYSC_IDLE_SMART_WKUP>; 1394 ti,syss-mask = <1>; 1395 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1396 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, 1397 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; 1398 clock-names = "fck", "dbclk"; 1399 #address-cells = <1>; 1400 #size-cells = <1>; 1401 ranges = <0x0 0x57000 0x1000>; 1402 1403 gpio3: gpio@0 { 1404 compatible = "ti,omap4-gpio"; 1405 reg = <0x0 0x200>; 1406 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1407 gpio-controller; 1408 #gpio-cells = <2>; 1409 interrupt-controller; 1410 #interrupt-cells = <2>; 1411 }; 1412 }; 1413 1414 target-module@59000 { /* 0x48059000, ap 17 16.0 */ 1415 compatible = "ti,sysc-omap2", "ti,sysc"; 1416 reg = <0x59000 0x4>, 1417 <0x59010 0x4>, 1418 <0x59114 0x4>; 1419 reg-names = "rev", "sysc", "syss"; 1420 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1421 SYSC_OMAP2_SOFTRESET | 1422 SYSC_OMAP2_AUTOIDLE)>; 1423 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1424 <SYSC_IDLE_NO>, 1425 <SYSC_IDLE_SMART>, 1426 <SYSC_IDLE_SMART_WKUP>; 1427 ti,syss-mask = <1>; 1428 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1429 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, 1430 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; 1431 clock-names = "fck", "dbclk"; 1432 #address-cells = <1>; 1433 #size-cells = <1>; 1434 ranges = <0x0 0x59000 0x1000>; 1435 1436 gpio4: gpio@0 { 1437 compatible = "ti,omap4-gpio"; 1438 reg = <0x0 0x200>; 1439 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1440 gpio-controller; 1441 #gpio-cells = <2>; 1442 interrupt-controller; 1443 #interrupt-cells = <2>; 1444 }; 1445 }; 1446 1447 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ 1448 compatible = "ti,sysc-omap2", "ti,sysc"; 1449 reg = <0x5b000 0x4>, 1450 <0x5b010 0x4>, 1451 <0x5b114 0x4>; 1452 reg-names = "rev", "sysc", "syss"; 1453 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1454 SYSC_OMAP2_SOFTRESET | 1455 SYSC_OMAP2_AUTOIDLE)>; 1456 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1457 <SYSC_IDLE_NO>, 1458 <SYSC_IDLE_SMART>, 1459 <SYSC_IDLE_SMART_WKUP>; 1460 ti,syss-mask = <1>; 1461 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1462 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, 1463 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; 1464 clock-names = "fck", "dbclk"; 1465 #address-cells = <1>; 1466 #size-cells = <1>; 1467 ranges = <0x0 0x5b000 0x1000>; 1468 1469 gpio5: gpio@0 { 1470 compatible = "ti,omap4-gpio"; 1471 reg = <0x0 0x200>; 1472 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1473 gpio-controller; 1474 #gpio-cells = <2>; 1475 interrupt-controller; 1476 #interrupt-cells = <2>; 1477 }; 1478 }; 1479 1480 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ 1481 compatible = "ti,sysc-omap2", "ti,sysc"; 1482 reg = <0x5d000 0x4>, 1483 <0x5d010 0x4>, 1484 <0x5d114 0x4>; 1485 reg-names = "rev", "sysc", "syss"; 1486 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1487 SYSC_OMAP2_SOFTRESET | 1488 SYSC_OMAP2_AUTOIDLE)>; 1489 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1490 <SYSC_IDLE_NO>, 1491 <SYSC_IDLE_SMART>, 1492 <SYSC_IDLE_SMART_WKUP>; 1493 ti,syss-mask = <1>; 1494 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1495 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, 1496 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; 1497 clock-names = "fck", "dbclk"; 1498 #address-cells = <1>; 1499 #size-cells = <1>; 1500 ranges = <0x0 0x5d000 0x1000>; 1501 1502 gpio6: gpio@0 { 1503 compatible = "ti,omap4-gpio"; 1504 reg = <0x0 0x200>; 1505 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1506 gpio-controller; 1507 #gpio-cells = <2>; 1508 interrupt-controller; 1509 #interrupt-cells = <2>; 1510 }; 1511 }; 1512 1513 target-module@60000 { /* 0x48060000, ap 23 32.0 */ 1514 compatible = "ti,sysc-omap2", "ti,sysc"; 1515 reg = <0x60000 0x8>, 1516 <0x60010 0x8>, 1517 <0x60090 0x8>; 1518 reg-names = "rev", "sysc", "syss"; 1519 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1520 SYSC_OMAP2_ENAWAKEUP | 1521 SYSC_OMAP2_SOFTRESET | 1522 SYSC_OMAP2_AUTOIDLE)>; 1523 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1524 <SYSC_IDLE_NO>, 1525 <SYSC_IDLE_SMART>, 1526 <SYSC_IDLE_SMART_WKUP>; 1527 ti,syss-mask = <1>; 1528 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1529 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; 1530 clock-names = "fck"; 1531 #address-cells = <1>; 1532 #size-cells = <1>; 1533 ranges = <0x0 0x60000 0x1000>; 1534 1535 i2c3: i2c@0 { 1536 compatible = "ti,omap4-i2c"; 1537 reg = <0x0 0x100>; 1538 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 status = "disabled"; 1542 }; 1543 }; 1544 1545 target-module@66000 { /* 0x48066000, ap 63 14.0 */ 1546 compatible = "ti,sysc-omap2", "ti,sysc"; 1547 reg = <0x66050 0x4>, 1548 <0x66054 0x4>, 1549 <0x66058 0x4>; 1550 reg-names = "rev", "sysc", "syss"; 1551 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1552 SYSC_OMAP2_SOFTRESET | 1553 SYSC_OMAP2_AUTOIDLE)>; 1554 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1555 <SYSC_IDLE_NO>, 1556 <SYSC_IDLE_SMART>, 1557 <SYSC_IDLE_SMART_WKUP>; 1558 ti,syss-mask = <1>; 1559 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1560 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; 1561 clock-names = "fck"; 1562 #address-cells = <1>; 1563 #size-cells = <1>; 1564 ranges = <0x0 0x66000 0x1000>; 1565 1566 uart5: serial@0 { 1567 compatible = "ti,dra742-uart"; 1568 reg = <0x0 0x100>; 1569 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1570 clock-frequency = <48000000>; 1571 status = "disabled"; 1572 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 1573 dma-names = "tx", "rx"; 1574 }; 1575 }; 1576 1577 target-module@68000 { /* 0x48068000, ap 53 1c.0 */ 1578 compatible = "ti,sysc-omap2", "ti,sysc"; 1579 reg = <0x68050 0x4>, 1580 <0x68054 0x4>, 1581 <0x68058 0x4>; 1582 reg-names = "rev", "sysc", "syss"; 1583 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1584 SYSC_OMAP2_SOFTRESET | 1585 SYSC_OMAP2_AUTOIDLE)>; 1586 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1587 <SYSC_IDLE_NO>, 1588 <SYSC_IDLE_SMART>, 1589 <SYSC_IDLE_SMART_WKUP>; 1590 ti,syss-mask = <1>; 1591 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 1592 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; 1593 clock-names = "fck"; 1594 #address-cells = <1>; 1595 #size-cells = <1>; 1596 ranges = <0x0 0x68000 0x1000>; 1597 1598 uart6: serial@0 { 1599 compatible = "ti,dra742-uart"; 1600 reg = <0x0 0x100>; 1601 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1602 clock-frequency = <48000000>; 1603 status = "disabled"; 1604 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 1605 dma-names = "tx", "rx"; 1606 }; 1607 }; 1608 1609 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ 1610 compatible = "ti,sysc-omap2", "ti,sysc"; 1611 reg = <0x6a050 0x4>, 1612 <0x6a054 0x4>, 1613 <0x6a058 0x4>; 1614 reg-names = "rev", "sysc", "syss"; 1615 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1616 SYSC_OMAP2_SOFTRESET | 1617 SYSC_OMAP2_AUTOIDLE)>; 1618 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1619 <SYSC_IDLE_NO>, 1620 <SYSC_IDLE_SMART>, 1621 <SYSC_IDLE_SMART_WKUP>; 1622 ti,syss-mask = <1>; 1623 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1624 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; 1625 clock-names = "fck"; 1626 #address-cells = <1>; 1627 #size-cells = <1>; 1628 ranges = <0x0 0x6a000 0x1000>; 1629 1630 uart1: serial@0 { 1631 compatible = "ti,dra742-uart"; 1632 reg = <0x0 0x100>; 1633 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1634 clock-frequency = <48000000>; 1635 status = "disabled"; 1636 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 1637 dma-names = "tx", "rx"; 1638 }; 1639 }; 1640 1641 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ 1642 compatible = "ti,sysc-omap2", "ti,sysc"; 1643 reg = <0x6c050 0x4>, 1644 <0x6c054 0x4>, 1645 <0x6c058 0x4>; 1646 reg-names = "rev", "sysc", "syss"; 1647 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1648 SYSC_OMAP2_SOFTRESET | 1649 SYSC_OMAP2_AUTOIDLE)>; 1650 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1651 <SYSC_IDLE_NO>, 1652 <SYSC_IDLE_SMART>, 1653 <SYSC_IDLE_SMART_WKUP>; 1654 ti,syss-mask = <1>; 1655 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1656 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; 1657 clock-names = "fck"; 1658 #address-cells = <1>; 1659 #size-cells = <1>; 1660 ranges = <0x0 0x6c000 0x1000>; 1661 1662 uart2: serial@0 { 1663 compatible = "ti,dra742-uart"; 1664 reg = <0x0 0x100>; 1665 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1666 clock-frequency = <48000000>; 1667 status = "disabled"; 1668 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 1669 dma-names = "tx", "rx"; 1670 }; 1671 }; 1672 1673 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ 1674 compatible = "ti,sysc-omap2", "ti,sysc"; 1675 reg = <0x6e050 0x4>, 1676 <0x6e054 0x4>, 1677 <0x6e058 0x4>; 1678 reg-names = "rev", "sysc", "syss"; 1679 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1680 SYSC_OMAP2_SOFTRESET | 1681 SYSC_OMAP2_AUTOIDLE)>; 1682 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1683 <SYSC_IDLE_NO>, 1684 <SYSC_IDLE_SMART>, 1685 <SYSC_IDLE_SMART_WKUP>; 1686 ti,syss-mask = <1>; 1687 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1688 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; 1689 clock-names = "fck"; 1690 #address-cells = <1>; 1691 #size-cells = <1>; 1692 ranges = <0x0 0x6e000 0x1000>; 1693 1694 uart4: serial@0 { 1695 compatible = "ti,dra742-uart"; 1696 reg = <0x0 0x100>; 1697 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1698 clock-frequency = <48000000>; 1699 status = "disabled"; 1700 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 1701 dma-names = "tx", "rx"; 1702 }; 1703 }; 1704 1705 target-module@70000 { /* 0x48070000, ap 30 22.0 */ 1706 compatible = "ti,sysc-omap2", "ti,sysc"; 1707 reg = <0x70000 0x8>, 1708 <0x70010 0x8>, 1709 <0x70090 0x8>; 1710 reg-names = "rev", "sysc", "syss"; 1711 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1712 SYSC_OMAP2_ENAWAKEUP | 1713 SYSC_OMAP2_SOFTRESET | 1714 SYSC_OMAP2_AUTOIDLE)>; 1715 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1716 <SYSC_IDLE_NO>, 1717 <SYSC_IDLE_SMART>, 1718 <SYSC_IDLE_SMART_WKUP>; 1719 ti,syss-mask = <1>; 1720 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1721 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; 1722 clock-names = "fck"; 1723 #address-cells = <1>; 1724 #size-cells = <1>; 1725 ranges = <0x0 0x70000 0x1000>; 1726 1727 i2c1: i2c@0 { 1728 compatible = "ti,omap4-i2c"; 1729 reg = <0x0 0x100>; 1730 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 status = "disabled"; 1734 }; 1735 }; 1736 1737 target-module@72000 { /* 0x48072000, ap 32 2a.0 */ 1738 compatible = "ti,sysc-omap2", "ti,sysc"; 1739 reg = <0x72000 0x8>, 1740 <0x72010 0x8>, 1741 <0x72090 0x8>; 1742 reg-names = "rev", "sysc", "syss"; 1743 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1744 SYSC_OMAP2_ENAWAKEUP | 1745 SYSC_OMAP2_SOFTRESET | 1746 SYSC_OMAP2_AUTOIDLE)>; 1747 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1748 <SYSC_IDLE_NO>, 1749 <SYSC_IDLE_SMART>, 1750 <SYSC_IDLE_SMART_WKUP>; 1751 ti,syss-mask = <1>; 1752 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1753 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; 1754 clock-names = "fck"; 1755 #address-cells = <1>; 1756 #size-cells = <1>; 1757 ranges = <0x0 0x72000 0x1000>; 1758 1759 i2c2: i2c@0 { 1760 compatible = "ti,omap4-i2c"; 1761 reg = <0x0 0x100>; 1762 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 status = "disabled"; 1766 }; 1767 }; 1768 1769 target-module@78000 { /* 0x48078000, ap 39 0a.0 */ 1770 compatible = "ti,sysc-omap2", "ti,sysc"; 1771 reg = <0x78000 0x4>, 1772 <0x78010 0x4>, 1773 <0x78014 0x4>; 1774 reg-names = "rev", "sysc", "syss"; 1775 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1776 SYSC_OMAP2_SOFTRESET | 1777 SYSC_OMAP2_AUTOIDLE)>; 1778 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1779 <SYSC_IDLE_NO>, 1780 <SYSC_IDLE_SMART>, 1781 <SYSC_IDLE_SMART_WKUP>; 1782 ti,syss-mask = <1>; 1783 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1784 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; 1785 clock-names = "fck"; 1786 #address-cells = <1>; 1787 #size-cells = <1>; 1788 ranges = <0x0 0x78000 0x1000>; 1789 1790 elm: elm@0 { 1791 compatible = "ti,am3352-elm"; 1792 reg = <0x0 0xfc0>; /* device IO registers */ 1793 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1794 status = "disabled"; 1795 }; 1796 }; 1797 1798 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ 1799 compatible = "ti,sysc-omap2", "ti,sysc"; 1800 reg = <0x7a000 0x8>, 1801 <0x7a010 0x8>, 1802 <0x7a090 0x8>; 1803 reg-names = "rev", "sysc", "syss"; 1804 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1805 SYSC_OMAP2_ENAWAKEUP | 1806 SYSC_OMAP2_SOFTRESET | 1807 SYSC_OMAP2_AUTOIDLE)>; 1808 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1809 <SYSC_IDLE_NO>, 1810 <SYSC_IDLE_SMART>, 1811 <SYSC_IDLE_SMART_WKUP>; 1812 ti,syss-mask = <1>; 1813 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1814 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; 1815 clock-names = "fck"; 1816 #address-cells = <1>; 1817 #size-cells = <1>; 1818 ranges = <0x0 0x7a000 0x1000>; 1819 1820 i2c4: i2c@0 { 1821 compatible = "ti,omap4-i2c"; 1822 reg = <0x0 0x100>; 1823 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 status = "disabled"; 1827 }; 1828 }; 1829 1830 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ 1831 compatible = "ti,sysc-omap2", "ti,sysc"; 1832 reg = <0x7c000 0x8>, 1833 <0x7c010 0x8>, 1834 <0x7c090 0x8>; 1835 reg-names = "rev", "sysc", "syss"; 1836 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1837 SYSC_OMAP2_ENAWAKEUP | 1838 SYSC_OMAP2_SOFTRESET | 1839 SYSC_OMAP2_AUTOIDLE)>; 1840 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1841 <SYSC_IDLE_NO>, 1842 <SYSC_IDLE_SMART>, 1843 <SYSC_IDLE_SMART_WKUP>; 1844 ti,syss-mask = <1>; 1845 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 1846 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; 1847 clock-names = "fck"; 1848 #address-cells = <1>; 1849 #size-cells = <1>; 1850 ranges = <0x0 0x7c000 0x1000>; 1851 1852 i2c5: i2c@0 { 1853 compatible = "ti,omap4-i2c"; 1854 reg = <0x0 0x100>; 1855 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1856 #address-cells = <1>; 1857 #size-cells = <0>; 1858 status = "disabled"; 1859 }; 1860 }; 1861 1862 target-module@86000 { /* 0x48086000, ap 41 5e.0 */ 1863 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1864 reg = <0x86000 0x4>, 1865 <0x86010 0x4>; 1866 reg-names = "rev", "sysc"; 1867 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1868 SYSC_OMAP4_SOFTRESET)>; 1869 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1870 <SYSC_IDLE_NO>, 1871 <SYSC_IDLE_SMART>, 1872 <SYSC_IDLE_SMART_WKUP>; 1873 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1874 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; 1875 clock-names = "fck"; 1876 #address-cells = <1>; 1877 #size-cells = <1>; 1878 ranges = <0x0 0x86000 0x1000>; 1879 1880 timer10: timer@0 { 1881 compatible = "ti,omap5430-timer"; 1882 reg = <0x0 0x80>; 1883 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>; 1884 clock-names = "fck", "timer_sys_ck"; 1885 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1886 }; 1887 }; 1888 1889 target-module@88000 { /* 0x48088000, ap 43 66.0 */ 1890 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1891 reg = <0x88000 0x4>, 1892 <0x88010 0x4>; 1893 reg-names = "rev", "sysc"; 1894 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1895 SYSC_OMAP4_SOFTRESET)>; 1896 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1897 <SYSC_IDLE_NO>, 1898 <SYSC_IDLE_SMART>, 1899 <SYSC_IDLE_SMART_WKUP>; 1900 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1901 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; 1902 clock-names = "fck"; 1903 #address-cells = <1>; 1904 #size-cells = <1>; 1905 ranges = <0x0 0x88000 0x1000>; 1906 1907 timer11: timer@0 { 1908 compatible = "ti,omap5430-timer"; 1909 reg = <0x0 0x80>; 1910 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>; 1911 clock-names = "fck", "timer_sys_ck"; 1912 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1913 }; 1914 }; 1915 1916 target-module@90000 { /* 0x48090000, ap 55 12.0 */ 1917 compatible = "ti,sysc-omap2", "ti,sysc"; 1918 reg = <0x91fe0 0x4>, 1919 <0x91fe4 0x4>; 1920 reg-names = "rev", "sysc"; 1921 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 1922 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1923 <SYSC_IDLE_NO>; 1924 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1925 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; 1926 clock-names = "fck"; 1927 #address-cells = <1>; 1928 #size-cells = <1>; 1929 ranges = <0x0 0x90000 0x2000>; 1930 1931 rng: rng@0 { 1932 compatible = "ti,omap4-rng"; 1933 reg = <0x0 0x2000>; 1934 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1935 clocks = <&l3_iclk_div>; 1936 clock-names = "fck"; 1937 }; 1938 }; 1939 1940 target-module@98000 { /* 0x48098000, ap 47 08.0 */ 1941 compatible = "ti,sysc-omap4", "ti,sysc"; 1942 reg = <0x98000 0x4>, 1943 <0x98010 0x4>; 1944 reg-names = "rev", "sysc"; 1945 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1946 SYSC_OMAP4_SOFTRESET)>; 1947 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1948 <SYSC_IDLE_NO>, 1949 <SYSC_IDLE_SMART>, 1950 <SYSC_IDLE_SMART_WKUP>; 1951 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1952 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; 1953 clock-names = "fck"; 1954 #address-cells = <1>; 1955 #size-cells = <1>; 1956 ranges = <0x0 0x98000 0x1000>; 1957 1958 mcspi1: spi@0 { 1959 compatible = "ti,omap4-mcspi"; 1960 reg = <0x0 0x200>; 1961 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 ti,spi-num-cs = <4>; 1965 dmas = <&sdma_xbar 35>, 1966 <&sdma_xbar 36>, 1967 <&sdma_xbar 37>, 1968 <&sdma_xbar 38>, 1969 <&sdma_xbar 39>, 1970 <&sdma_xbar 40>, 1971 <&sdma_xbar 41>, 1972 <&sdma_xbar 42>; 1973 dma-names = "tx0", "rx0", "tx1", "rx1", 1974 "tx2", "rx2", "tx3", "rx3"; 1975 status = "disabled"; 1976 }; 1977 }; 1978 1979 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ 1980 compatible = "ti,sysc-omap4", "ti,sysc"; 1981 reg = <0x9a000 0x4>, 1982 <0x9a010 0x4>; 1983 reg-names = "rev", "sysc"; 1984 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1985 SYSC_OMAP4_SOFTRESET)>; 1986 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1987 <SYSC_IDLE_NO>, 1988 <SYSC_IDLE_SMART>, 1989 <SYSC_IDLE_SMART_WKUP>; 1990 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1991 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; 1992 clock-names = "fck"; 1993 #address-cells = <1>; 1994 #size-cells = <1>; 1995 ranges = <0x0 0x9a000 0x1000>; 1996 1997 mcspi2: spi@0 { 1998 compatible = "ti,omap4-mcspi"; 1999 reg = <0x0 0x200>; 2000 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 2001 #address-cells = <1>; 2002 #size-cells = <0>; 2003 ti,spi-num-cs = <2>; 2004 dmas = <&sdma_xbar 43>, 2005 <&sdma_xbar 44>, 2006 <&sdma_xbar 45>, 2007 <&sdma_xbar 46>; 2008 dma-names = "tx0", "rx0", "tx1", "rx1"; 2009 status = "disabled"; 2010 }; 2011 }; 2012 2013 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ 2014 compatible = "ti,sysc-omap4", "ti,sysc"; 2015 reg = <0x9c000 0x4>, 2016 <0x9c010 0x4>; 2017 reg-names = "rev", "sysc"; 2018 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2019 SYSC_OMAP4_SOFTRESET)>; 2020 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2021 <SYSC_IDLE_NO>, 2022 <SYSC_IDLE_SMART>, 2023 <SYSC_IDLE_SMART_WKUP>; 2024 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2025 <SYSC_IDLE_NO>, 2026 <SYSC_IDLE_SMART>, 2027 <SYSC_IDLE_SMART_WKUP>; 2028 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 2029 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; 2030 clock-names = "fck"; 2031 #address-cells = <1>; 2032 #size-cells = <1>; 2033 ranges = <0x0 0x9c000 0x1000>; 2034 2035 mmc1: mmc@0 { 2036 compatible = "ti,dra7-sdhci"; 2037 reg = <0x0 0x400>; 2038 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2039 status = "disabled"; 2040 pbias-supply = <&pbias_mmc_reg>; 2041 max-frequency = <192000000>; 2042 mmc-ddr-1_8v; 2043 mmc-ddr-3_3v; 2044 }; 2045 }; 2046 2047 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ 2048 compatible = "ti,sysc"; 2049 status = "disabled"; 2050 #address-cells = <1>; 2051 #size-cells = <1>; 2052 ranges = <0x0 0xa2000 0x1000>; 2053 }; 2054 2055 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ 2056 compatible = "ti,sysc"; 2057 status = "disabled"; 2058 #address-cells = <1>; 2059 #size-cells = <1>; 2060 ranges = <0x00000000 0x000a4000 0x00001000>, 2061 <0x00001000 0x000a5000 0x00001000>; 2062 }; 2063 2064 des_target: target-module@a5000 { /* 0x480a5000 */ 2065 compatible = "ti,sysc-omap2", "ti,sysc"; 2066 reg = <0xa5030 0x4>, 2067 <0xa5034 0x4>, 2068 <0xa5038 0x4>; 2069 reg-names = "rev", "sysc", "syss"; 2070 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2071 SYSC_OMAP2_AUTOIDLE)>; 2072 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2073 <SYSC_IDLE_NO>, 2074 <SYSC_IDLE_SMART>, 2075 <SYSC_IDLE_SMART_WKUP>; 2076 ti,syss-mask = <1>; 2077 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 2078 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>; 2079 clock-names = "fck"; 2080 #address-cells = <1>; 2081 #size-cells = <1>; 2082 ranges = <0 0xa5000 0x00001000>; 2083 2084 des: des@0 { 2085 compatible = "ti,omap4-des"; 2086 reg = <0 0xa0>; 2087 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 2088 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; 2089 dma-names = "tx", "rx"; 2090 clocks = <&l3_iclk_div>; 2091 clock-names = "fck"; 2092 }; 2093 }; 2094 2095 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ 2096 compatible = "ti,sysc"; 2097 status = "disabled"; 2098 #address-cells = <1>; 2099 #size-cells = <1>; 2100 ranges = <0x0 0xa8000 0x4000>; 2101 }; 2102 2103 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ 2104 compatible = "ti,sysc-omap4", "ti,sysc"; 2105 reg = <0xad000 0x4>, 2106 <0xad010 0x4>; 2107 reg-names = "rev", "sysc"; 2108 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2109 SYSC_OMAP4_SOFTRESET)>; 2110 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2111 <SYSC_IDLE_NO>, 2112 <SYSC_IDLE_SMART>, 2113 <SYSC_IDLE_SMART_WKUP>; 2114 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2115 <SYSC_IDLE_NO>, 2116 <SYSC_IDLE_SMART>, 2117 <SYSC_IDLE_SMART_WKUP>; 2118 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2119 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; 2120 clock-names = "fck"; 2121 #address-cells = <1>; 2122 #size-cells = <1>; 2123 ranges = <0x0 0xad000 0x1000>; 2124 2125 mmc3: mmc@0 { 2126 compatible = "ti,dra7-sdhci"; 2127 reg = <0x0 0x400>; 2128 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 2129 status = "disabled"; 2130 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ 2131 max-frequency = <64000000>; 2132 /* SDMA is not supported */ 2133 sdhci-caps-mask = <0x0 0x400000>; 2134 }; 2135 }; 2136 2137 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ 2138 compatible = "ti,sysc-omap2", "ti,sysc"; 2139 reg = <0xb2000 0x4>, 2140 <0xb2014 0x4>, 2141 <0xb2018 0x4>; 2142 reg-names = "rev", "sysc", "syss"; 2143 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2144 SYSC_OMAP2_AUTOIDLE)>; 2145 ti,syss-mask = <1>; 2146 ti,no-reset-on-init; 2147 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2148 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; 2149 clock-names = "fck"; 2150 #address-cells = <1>; 2151 #size-cells = <1>; 2152 ranges = <0x0 0xb2000 0x1000>; 2153 2154 hdqw1w: 1w@0 { 2155 compatible = "ti,omap3-1w"; 2156 reg = <0x0 0x1000>; 2157 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2158 }; 2159 }; 2160 2161 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ 2162 compatible = "ti,sysc-omap4", "ti,sysc"; 2163 reg = <0xb4000 0x4>, 2164 <0xb4010 0x4>; 2165 reg-names = "rev", "sysc"; 2166 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2167 SYSC_OMAP4_SOFTRESET)>; 2168 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2169 <SYSC_IDLE_NO>, 2170 <SYSC_IDLE_SMART>, 2171 <SYSC_IDLE_SMART_WKUP>; 2172 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2173 <SYSC_IDLE_NO>, 2174 <SYSC_IDLE_SMART>, 2175 <SYSC_IDLE_SMART_WKUP>; 2176 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 2177 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; 2178 clock-names = "fck"; 2179 #address-cells = <1>; 2180 #size-cells = <1>; 2181 ranges = <0x0 0xb4000 0x1000>; 2182 2183 mmc2: mmc@0 { 2184 compatible = "ti,dra7-sdhci"; 2185 reg = <0x0 0x400>; 2186 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2187 status = "disabled"; 2188 max-frequency = <192000000>; 2189 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ 2190 sdhci-caps-mask = <0x7 0x0>; 2191 mmc-hs200-1_8v; 2192 mmc-ddr-1_8v; 2193 mmc-ddr-3_3v; 2194 }; 2195 }; 2196 2197 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ 2198 compatible = "ti,sysc-omap4", "ti,sysc"; 2199 reg = <0xb8000 0x4>, 2200 <0xb8010 0x4>; 2201 reg-names = "rev", "sysc"; 2202 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2203 SYSC_OMAP4_SOFTRESET)>; 2204 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2205 <SYSC_IDLE_NO>, 2206 <SYSC_IDLE_SMART>, 2207 <SYSC_IDLE_SMART_WKUP>; 2208 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2209 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; 2210 clock-names = "fck"; 2211 #address-cells = <1>; 2212 #size-cells = <1>; 2213 ranges = <0x0 0xb8000 0x1000>; 2214 2215 mcspi3: spi@0 { 2216 compatible = "ti,omap4-mcspi"; 2217 reg = <0x0 0x200>; 2218 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2219 #address-cells = <1>; 2220 #size-cells = <0>; 2221 ti,spi-num-cs = <2>; 2222 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 2223 dma-names = "tx0", "rx0"; 2224 status = "disabled"; 2225 }; 2226 }; 2227 2228 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ 2229 compatible = "ti,sysc-omap4", "ti,sysc"; 2230 reg = <0xba000 0x4>, 2231 <0xba010 0x4>; 2232 reg-names = "rev", "sysc"; 2233 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2234 SYSC_OMAP4_SOFTRESET)>; 2235 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2236 <SYSC_IDLE_NO>, 2237 <SYSC_IDLE_SMART>, 2238 <SYSC_IDLE_SMART_WKUP>; 2239 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2240 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; 2241 clock-names = "fck"; 2242 #address-cells = <1>; 2243 #size-cells = <1>; 2244 ranges = <0x0 0xba000 0x1000>; 2245 2246 mcspi4: spi@0 { 2247 compatible = "ti,omap4-mcspi"; 2248 reg = <0x0 0x200>; 2249 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 2250 #address-cells = <1>; 2251 #size-cells = <0>; 2252 ti,spi-num-cs = <1>; 2253 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 2254 dma-names = "tx0", "rx0"; 2255 status = "disabled"; 2256 }; 2257 }; 2258 2259 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ 2260 compatible = "ti,sysc-omap4", "ti,sysc"; 2261 reg = <0xd1000 0x4>, 2262 <0xd1010 0x4>; 2263 reg-names = "rev", "sysc"; 2264 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2265 SYSC_OMAP4_SOFTRESET)>; 2266 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2267 <SYSC_IDLE_NO>, 2268 <SYSC_IDLE_SMART>, 2269 <SYSC_IDLE_SMART_WKUP>; 2270 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2271 <SYSC_IDLE_NO>, 2272 <SYSC_IDLE_SMART>, 2273 <SYSC_IDLE_SMART_WKUP>; 2274 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2275 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; 2276 clock-names = "fck"; 2277 #address-cells = <1>; 2278 #size-cells = <1>; 2279 ranges = <0x0 0xd1000 0x1000>; 2280 2281 mmc4: mmc@0 { 2282 compatible = "ti,dra7-sdhci"; 2283 reg = <0x0 0x400>; 2284 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2285 status = "disabled"; 2286 max-frequency = <192000000>; 2287 /* SDMA is not supported */ 2288 sdhci-caps-mask = <0x0 0x400000>; 2289 }; 2290 }; 2291 2292 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ 2293 compatible = "ti,sysc"; 2294 status = "disabled"; 2295 #address-cells = <1>; 2296 #size-cells = <1>; 2297 ranges = <0x0 0xd5000 0x1000>; 2298 }; 2299 }; 2300 2301 segment@200000 { /* 0x48200000 */ 2302 compatible = "simple-pm-bus"; 2303 #address-cells = <1>; 2304 #size-cells = <1>; 2305 }; 2306}; 2307 2308&l4_per2 { /* 0x48400000 */ 2309 compatible = "ti,dra7-l4-per2", "simple-pm-bus"; 2310 power-domains = <&prm_l4per>; 2311 clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>; 2312 clock-names = "fck"; 2313 reg = <0x48400000 0x800>, 2314 <0x48400800 0x800>, 2315 <0x48401000 0x400>, 2316 <0x48401400 0x400>, 2317 <0x48401800 0x400>; 2318 reg-names = "ap", "la", "ia0", "ia1", "ia2"; 2319 #address-cells = <1>; 2320 #size-cells = <1>; 2321 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ 2322 <0x45800000 0x45800000 0x400000>, /* L3 data port */ 2323 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ 2324 <0x46000000 0x46000000 0x400000>, /* L3 data port */ 2325 <0x48436000 0x48436000 0x400000>, /* L3 data port */ 2326 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ 2327 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ 2328 <0x48450000 0x48450000 0x400000>, /* L3 data port */ 2329 <0x48454000 0x48454000 0x400000>; /* L3 data port */ 2330 2331 segment@0 { /* 0x48400000 */ 2332 compatible = "simple-pm-bus"; 2333 #address-cells = <1>; 2334 #size-cells = <1>; 2335 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 2336 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 2337 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 2338 <0x00084000 0x00084000 0x004000>, /* ap 3 */ 2339 <0x00001400 0x00001400 0x000400>, /* ap 4 */ 2340 <0x00001800 0x00001800 0x000400>, /* ap 5 */ 2341 <0x00088000 0x00088000 0x001000>, /* ap 6 */ 2342 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ 2343 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ 2344 <0x00060000 0x00060000 0x002000>, /* ap 9 */ 2345 <0x00062000 0x00062000 0x001000>, /* ap 10 */ 2346 <0x00064000 0x00064000 0x002000>, /* ap 11 */ 2347 <0x00066000 0x00066000 0x001000>, /* ap 12 */ 2348 <0x00068000 0x00068000 0x002000>, /* ap 13 */ 2349 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ 2350 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ 2351 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ 2352 <0x00036000 0x00036000 0x001000>, /* ap 17 */ 2353 <0x00037000 0x00037000 0x001000>, /* ap 18 */ 2354 <0x00070000 0x00070000 0x002000>, /* ap 19 */ 2355 <0x00072000 0x00072000 0x001000>, /* ap 20 */ 2356 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ 2357 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ 2358 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 2359 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ 2360 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ 2361 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ 2362 <0x00040000 0x00040000 0x001000>, /* ap 27 */ 2363 <0x00041000 0x00041000 0x001000>, /* ap 28 */ 2364 <0x00042000 0x00042000 0x001000>, /* ap 29 */ 2365 <0x00043000 0x00043000 0x001000>, /* ap 30 */ 2366 <0x00080000 0x00080000 0x002000>, /* ap 31 */ 2367 <0x00082000 0x00082000 0x001000>, /* ap 32 */ 2368 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ 2369 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ 2370 <0x00074000 0x00074000 0x002000>, /* ap 35 */ 2371 <0x00076000 0x00076000 0x001000>, /* ap 36 */ 2372 <0x00050000 0x00050000 0x001000>, /* ap 37 */ 2373 <0x00051000 0x00051000 0x001000>, /* ap 38 */ 2374 <0x00078000 0x00078000 0x002000>, /* ap 39 */ 2375 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ 2376 <0x00054000 0x00054000 0x001000>, /* ap 41 */ 2377 <0x00055000 0x00055000 0x001000>, /* ap 42 */ 2378 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ 2379 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ 2380 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ 2381 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ 2382 <0x00020000 0x00020000 0x001000>, /* ap 47 */ 2383 <0x00021000 0x00021000 0x001000>, /* ap 48 */ 2384 <0x00022000 0x00022000 0x001000>, /* ap 49 */ 2385 <0x00023000 0x00023000 0x001000>, /* ap 50 */ 2386 <0x00024000 0x00024000 0x001000>, /* ap 51 */ 2387 <0x00025000 0x00025000 0x001000>, /* ap 52 */ 2388 <0x00046000 0x00046000 0x001000>, /* ap 53 */ 2389 <0x00047000 0x00047000 0x001000>, /* ap 54 */ 2390 <0x00048000 0x00048000 0x001000>, /* ap 55 */ 2391 <0x00049000 0x00049000 0x001000>, /* ap 56 */ 2392 <0x00058000 0x00058000 0x002000>, /* ap 57 */ 2393 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ 2394 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ 2395 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ 2396 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ 2397 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ 2398 <0x45800000 0x45800000 0x400000>, /* L3 data port */ 2399 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ 2400 <0x46000000 0x46000000 0x400000>, /* L3 data port */ 2401 <0x48436000 0x48436000 0x400000>, /* L3 data port */ 2402 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ 2403 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ 2404 <0x48450000 0x48450000 0x400000>, /* L3 data port */ 2405 <0x48454000 0x48454000 0x400000>; /* L3 data port */ 2406 2407 target-module@20000 { /* 0x48420000, ap 47 02.0 */ 2408 compatible = "ti,sysc-omap2", "ti,sysc"; 2409 reg = <0x20050 0x4>, 2410 <0x20054 0x4>, 2411 <0x20058 0x4>; 2412 reg-names = "rev", "sysc", "syss"; 2413 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2414 SYSC_OMAP2_SOFTRESET | 2415 SYSC_OMAP2_AUTOIDLE)>; 2416 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2417 <SYSC_IDLE_NO>, 2418 <SYSC_IDLE_SMART>, 2419 <SYSC_IDLE_SMART_WKUP>; 2420 ti,syss-mask = <1>; 2421 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2422 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; 2423 clock-names = "fck"; 2424 #address-cells = <1>; 2425 #size-cells = <1>; 2426 ranges = <0x0 0x20000 0x1000>; 2427 2428 uart7: serial@0 { 2429 compatible = "ti,dra742-uart"; 2430 reg = <0x0 0x100>; 2431 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 2432 clock-frequency = <48000000>; 2433 status = "disabled"; 2434 }; 2435 }; 2436 2437 target-module@22000 { /* 0x48422000, ap 49 0a.0 */ 2438 compatible = "ti,sysc-omap2", "ti,sysc"; 2439 reg = <0x22050 0x4>, 2440 <0x22054 0x4>, 2441 <0x22058 0x4>; 2442 reg-names = "rev", "sysc", "syss"; 2443 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2444 SYSC_OMAP2_SOFTRESET | 2445 SYSC_OMAP2_AUTOIDLE)>; 2446 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2447 <SYSC_IDLE_NO>, 2448 <SYSC_IDLE_SMART>, 2449 <SYSC_IDLE_SMART_WKUP>; 2450 ti,syss-mask = <1>; 2451 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2452 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; 2453 clock-names = "fck"; 2454 #address-cells = <1>; 2455 #size-cells = <1>; 2456 ranges = <0x0 0x22000 0x1000>; 2457 2458 uart8: serial@0 { 2459 compatible = "ti,dra742-uart"; 2460 reg = <0x0 0x100>; 2461 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 2462 clock-frequency = <48000000>; 2463 status = "disabled"; 2464 }; 2465 }; 2466 2467 target-module@24000 { /* 0x48424000, ap 51 12.0 */ 2468 compatible = "ti,sysc-omap2", "ti,sysc"; 2469 reg = <0x24050 0x4>, 2470 <0x24054 0x4>, 2471 <0x24058 0x4>; 2472 reg-names = "rev", "sysc", "syss"; 2473 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2474 SYSC_OMAP2_SOFTRESET | 2475 SYSC_OMAP2_AUTOIDLE)>; 2476 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2477 <SYSC_IDLE_NO>, 2478 <SYSC_IDLE_SMART>, 2479 <SYSC_IDLE_SMART_WKUP>; 2480 ti,syss-mask = <1>; 2481 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2482 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; 2483 clock-names = "fck"; 2484 #address-cells = <1>; 2485 #size-cells = <1>; 2486 ranges = <0x0 0x24000 0x1000>; 2487 2488 uart9: serial@0 { 2489 compatible = "ti,dra742-uart"; 2490 reg = <0x0 0x100>; 2491 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 2492 clock-frequency = <48000000>; 2493 status = "disabled"; 2494 }; 2495 }; 2496 2497 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ 2498 compatible = "ti,sysc"; 2499 status = "disabled"; 2500 #address-cells = <1>; 2501 #size-cells = <1>; 2502 ranges = <0x0 0x2c000 0x1000>; 2503 }; 2504 2505 target-module@36000 { /* 0x48436000, ap 17 06.0 */ 2506 compatible = "ti,sysc"; 2507 status = "disabled"; 2508 #address-cells = <1>; 2509 #size-cells = <1>; 2510 ranges = <0x0 0x36000 0x1000>; 2511 }; 2512 2513 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ 2514 compatible = "ti,sysc"; 2515 status = "disabled"; 2516 #address-cells = <1>; 2517 #size-cells = <1>; 2518 ranges = <0x0 0x3a000 0x1000>; 2519 }; 2520 2521 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ 2522 compatible = "ti,sysc-omap4", "ti,sysc"; 2523 reg = <0x3c000 0x4>; 2524 reg-names = "rev"; 2525 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; 2526 clock-names = "fck"; 2527 #address-cells = <1>; 2528 #size-cells = <1>; 2529 ranges = <0x0 0x3c000 0x1000>; 2530 2531 atl: atl@0 { 2532 compatible = "ti,dra7-atl"; 2533 reg = <0x0 0x3ff>; 2534 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 2535 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 2536 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 2537 clock-names = "fck"; 2538 status = "disabled"; 2539 }; 2540 }; 2541 2542 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ 2543 compatible = "ti,sysc-omap4", "ti,sysc"; 2544 reg = <0x3e000 0x4>, 2545 <0x3e004 0x4>; 2546 reg-names = "rev", "sysc"; 2547 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2548 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2549 <SYSC_IDLE_NO>, 2550 <SYSC_IDLE_SMART>; 2551 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2552 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; 2553 clock-names = "fck"; 2554 #address-cells = <1>; 2555 #size-cells = <1>; 2556 ranges = <0x0 0x3e000 0x1000>; 2557 2558 epwmss0: epwmss@0 { 2559 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2560 reg = <0x0 0x30>; 2561 #address-cells = <1>; 2562 #size-cells = <1>; 2563 status = "disabled"; 2564 ranges = <0 0 0x1000>; 2565 2566 ecap0: pwm@100 { 2567 compatible = "ti,dra746-ecap", 2568 "ti,am3352-ecap"; 2569 #pwm-cells = <3>; 2570 reg = <0x100 0x80>; 2571 clocks = <&l4_root_clk_div>; 2572 clock-names = "fck"; 2573 status = "disabled"; 2574 }; 2575 2576 ehrpwm0: pwm@200 { 2577 compatible = "ti,dra746-ehrpwm", 2578 "ti,am3352-ehrpwm"; 2579 #pwm-cells = <3>; 2580 reg = <0x200 0x80>; 2581 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 2582 clock-names = "tbclk", "fck"; 2583 status = "disabled"; 2584 }; 2585 }; 2586 }; 2587 2588 target-module@40000 { /* 0x48440000, ap 27 38.0 */ 2589 compatible = "ti,sysc-omap4", "ti,sysc"; 2590 reg = <0x40000 0x4>, 2591 <0x40004 0x4>; 2592 reg-names = "rev", "sysc"; 2593 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2594 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2595 <SYSC_IDLE_NO>, 2596 <SYSC_IDLE_SMART>; 2597 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2598 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; 2599 clock-names = "fck"; 2600 #address-cells = <1>; 2601 #size-cells = <1>; 2602 ranges = <0x0 0x40000 0x1000>; 2603 2604 epwmss1: epwmss@0 { 2605 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2606 reg = <0x0 0x30>; 2607 #address-cells = <1>; 2608 #size-cells = <1>; 2609 status = "disabled"; 2610 ranges = <0 0 0x1000>; 2611 2612 ecap1: pwm@100 { 2613 compatible = "ti,dra746-ecap", 2614 "ti,am3352-ecap"; 2615 #pwm-cells = <3>; 2616 reg = <0x100 0x80>; 2617 clocks = <&l4_root_clk_div>; 2618 clock-names = "fck"; 2619 status = "disabled"; 2620 }; 2621 2622 ehrpwm1: pwm@200 { 2623 compatible = "ti,dra746-ehrpwm", 2624 "ti,am3352-ehrpwm"; 2625 #pwm-cells = <3>; 2626 reg = <0x200 0x80>; 2627 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 2628 clock-names = "tbclk", "fck"; 2629 status = "disabled"; 2630 }; 2631 }; 2632 }; 2633 2634 target-module@42000 { /* 0x48442000, ap 29 20.0 */ 2635 compatible = "ti,sysc-omap4", "ti,sysc"; 2636 reg = <0x42000 0x4>, 2637 <0x42004 0x4>; 2638 reg-names = "rev", "sysc"; 2639 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2640 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2641 <SYSC_IDLE_NO>, 2642 <SYSC_IDLE_SMART>; 2643 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2644 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; 2645 clock-names = "fck"; 2646 #address-cells = <1>; 2647 #size-cells = <1>; 2648 ranges = <0x0 0x42000 0x1000>; 2649 2650 epwmss2: epwmss@0 { 2651 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2652 reg = <0x0 0x30>; 2653 #address-cells = <1>; 2654 #size-cells = <1>; 2655 status = "disabled"; 2656 ranges = <0 0 0x1000>; 2657 2658 ecap2: pwm@100 { 2659 compatible = "ti,dra746-ecap", 2660 "ti,am3352-ecap"; 2661 #pwm-cells = <3>; 2662 reg = <0x100 0x80>; 2663 clocks = <&l4_root_clk_div>; 2664 clock-names = "fck"; 2665 status = "disabled"; 2666 }; 2667 2668 ehrpwm2: pwm@200 { 2669 compatible = "ti,dra746-ehrpwm", 2670 "ti,am3352-ehrpwm"; 2671 #pwm-cells = <3>; 2672 reg = <0x200 0x80>; 2673 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 2674 clock-names = "tbclk", "fck"; 2675 status = "disabled"; 2676 }; 2677 }; 2678 }; 2679 2680 target-module@46000 { /* 0x48446000, ap 53 40.0 */ 2681 compatible = "ti,sysc"; 2682 status = "disabled"; 2683 #address-cells = <1>; 2684 #size-cells = <1>; 2685 ranges = <0x0 0x46000 0x1000>; 2686 }; 2687 2688 target-module@48000 { /* 0x48448000, ap 55 48.0 */ 2689 compatible = "ti,sysc"; 2690 status = "disabled"; 2691 #address-cells = <1>; 2692 #size-cells = <1>; 2693 ranges = <0x0 0x48000 0x1000>; 2694 }; 2695 2696 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ 2697 compatible = "ti,sysc"; 2698 status = "disabled"; 2699 #address-cells = <1>; 2700 #size-cells = <1>; 2701 ranges = <0x0 0x4a000 0x1000>; 2702 }; 2703 2704 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ 2705 compatible = "ti,sysc"; 2706 status = "disabled"; 2707 #address-cells = <1>; 2708 #size-cells = <1>; 2709 ranges = <0x0 0x4c000 0x1000>; 2710 }; 2711 2712 target-module@50000 { /* 0x48450000, ap 37 24.0 */ 2713 compatible = "ti,sysc"; 2714 status = "disabled"; 2715 #address-cells = <1>; 2716 #size-cells = <1>; 2717 ranges = <0x0 0x50000 0x1000>; 2718 }; 2719 2720 target-module@54000 { /* 0x48454000, ap 41 2c.0 */ 2721 compatible = "ti,sysc"; 2722 status = "disabled"; 2723 #address-cells = <1>; 2724 #size-cells = <1>; 2725 ranges = <0x0 0x54000 0x1000>; 2726 }; 2727 2728 target-module@58000 { /* 0x48458000, ap 57 28.0 */ 2729 compatible = "ti,sysc"; 2730 status = "disabled"; 2731 #address-cells = <1>; 2732 #size-cells = <1>; 2733 ranges = <0x0 0x58000 0x2000>; 2734 }; 2735 2736 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ 2737 compatible = "ti,sysc"; 2738 status = "disabled"; 2739 #address-cells = <1>; 2740 #size-cells = <1>; 2741 ranges = <0x0 0x5b000 0x1000>; 2742 }; 2743 2744 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ 2745 compatible = "ti,sysc"; 2746 status = "disabled"; 2747 #address-cells = <1>; 2748 #size-cells = <1>; 2749 ranges = <0x0 0x5d000 0x1000>; 2750 }; 2751 2752 target-module@60000 { /* 0x48460000, ap 9 0e.0 */ 2753 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2754 reg = <0x60000 0x4>, 2755 <0x60004 0x4>; 2756 reg-names = "rev", "sysc"; 2757 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2758 <SYSC_IDLE_NO>, 2759 <SYSC_IDLE_SMART>; 2760 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 2761 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, 2762 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2763 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2764 clock-names = "fck", "ahclkx", "ahclkr"; 2765 #address-cells = <1>; 2766 #size-cells = <1>; 2767 ranges = <0x0 0x60000 0x2000>, 2768 <0x45800000 0x45800000 0x400000>; 2769 2770 mcasp1: mcasp@0 { 2771 compatible = "ti,dra7-mcasp-audio"; 2772 reg = <0x0 0x2000>, 2773 <0x45800000 0x1000>; /* L3 data port */ 2774 reg-names = "mpu","dat"; 2775 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2776 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2777 interrupt-names = "tx", "rx"; 2778 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 2779 dma-names = "tx", "rx"; 2780 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, 2781 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2782 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2783 clock-names = "fck", "ahclkx", "ahclkr"; 2784 status = "disabled"; 2785 }; 2786 }; 2787 2788 target-module@64000 { /* 0x48464000, ap 11 1e.0 */ 2789 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2790 reg = <0x64000 0x4>, 2791 <0x64004 0x4>; 2792 reg-names = "rev", "sysc"; 2793 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2794 <SYSC_IDLE_NO>, 2795 <SYSC_IDLE_SMART>; 2796 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2797 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, 2798 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, 2799 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2800 clock-names = "fck", "ahclkx", "ahclkr"; 2801 #address-cells = <1>; 2802 #size-cells = <1>; 2803 ranges = <0x0 0x64000 0x2000>, 2804 <0x45c00000 0x45c00000 0x400000>; 2805 2806 mcasp2: mcasp@0 { 2807 compatible = "ti,dra7-mcasp-audio"; 2808 reg = <0x0 0x2000>, 2809 <0x45c00000 0x1000>; /* L3 data port */ 2810 reg-names = "mpu","dat"; 2811 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2812 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2813 interrupt-names = "tx", "rx"; 2814 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 2815 dma-names = "tx", "rx"; 2816 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, 2817 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2818 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2819 clock-names = "fck", "ahclkx", "ahclkr"; 2820 status = "disabled"; 2821 }; 2822 }; 2823 2824 target-module@68000 { /* 0x48468000, ap 13 26.0 */ 2825 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2826 reg = <0x68000 0x4>, 2827 <0x68004 0x4>; 2828 reg-names = "rev", "sysc"; 2829 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2830 <SYSC_IDLE_NO>, 2831 <SYSC_IDLE_SMART>; 2832 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2833 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2834 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2835 clock-names = "fck", "ahclkx"; 2836 #address-cells = <1>; 2837 #size-cells = <1>; 2838 ranges = <0x0 0x68000 0x2000>, 2839 <0x46000000 0x46000000 0x400000>; 2840 2841 mcasp3: mcasp@0 { 2842 compatible = "ti,dra7-mcasp-audio"; 2843 reg = <0x0 0x2000>, 2844 <0x46000000 0x1000>; /* L3 data port */ 2845 reg-names = "mpu","dat"; 2846 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2848 interrupt-names = "tx", "rx"; 2849 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 2850 dma-names = "tx", "rx"; 2851 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2852 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2853 clock-names = "fck", "ahclkx"; 2854 status = "disabled"; 2855 }; 2856 }; 2857 2858 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ 2859 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2860 reg = <0x6c000 0x4>, 2861 <0x6c004 0x4>; 2862 reg-names = "rev", "sysc"; 2863 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2864 <SYSC_IDLE_NO>, 2865 <SYSC_IDLE_SMART>; 2866 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2867 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2868 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2869 clock-names = "fck", "ahclkx"; 2870 #address-cells = <1>; 2871 #size-cells = <1>; 2872 ranges = <0x0 0x6c000 0x2000>, 2873 <0x48436000 0x48436000 0x400000>; 2874 2875 mcasp4: mcasp@0 { 2876 compatible = "ti,dra7-mcasp-audio"; 2877 reg = <0x0 0x2000>, 2878 <0x48436000 0x1000>; /* L3 data port */ 2879 reg-names = "mpu","dat"; 2880 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 2881 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2882 interrupt-names = "tx", "rx"; 2883 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 2884 dma-names = "tx", "rx"; 2885 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2886 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2887 clock-names = "fck", "ahclkx"; 2888 status = "disabled"; 2889 }; 2890 }; 2891 2892 target-module@70000 { /* 0x48470000, ap 19 36.0 */ 2893 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2894 reg = <0x70000 0x4>, 2895 <0x70004 0x4>; 2896 reg-names = "rev", "sysc"; 2897 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2898 <SYSC_IDLE_NO>, 2899 <SYSC_IDLE_SMART>; 2900 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2901 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2902 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2903 clock-names = "fck", "ahclkx"; 2904 #address-cells = <1>; 2905 #size-cells = <1>; 2906 ranges = <0x0 0x70000 0x2000>, 2907 <0x4843a000 0x4843a000 0x400000>; 2908 2909 mcasp5: mcasp@0 { 2910 compatible = "ti,dra7-mcasp-audio"; 2911 reg = <0x0 0x2000>, 2912 <0x4843a000 0x1000>; /* L3 data port */ 2913 reg-names = "mpu","dat"; 2914 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 2915 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 2916 interrupt-names = "tx", "rx"; 2917 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 2918 dma-names = "tx", "rx"; 2919 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2920 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2921 clock-names = "fck", "ahclkx"; 2922 status = "disabled"; 2923 }; 2924 }; 2925 2926 target-module@74000 { /* 0x48474000, ap 35 14.0 */ 2927 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2928 reg = <0x74000 0x4>, 2929 <0x74004 0x4>; 2930 reg-names = "rev", "sysc"; 2931 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2932 <SYSC_IDLE_NO>, 2933 <SYSC_IDLE_SMART>; 2934 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2935 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2936 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2937 clock-names = "fck", "ahclkx"; 2938 #address-cells = <1>; 2939 #size-cells = <1>; 2940 ranges = <0x0 0x74000 0x2000>, 2941 <0x4844c000 0x4844c000 0x400000>; 2942 2943 mcasp6: mcasp@0 { 2944 compatible = "ti,dra7-mcasp-audio"; 2945 reg = <0x0 0x2000>, 2946 <0x4844c000 0x1000>; /* L3 data port */ 2947 reg-names = "mpu","dat"; 2948 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 2950 interrupt-names = "tx", "rx"; 2951 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 2952 dma-names = "tx", "rx"; 2953 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2954 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2955 clock-names = "fck", "ahclkx"; 2956 status = "disabled"; 2957 }; 2958 }; 2959 2960 target-module@78000 { /* 0x48478000, ap 39 0c.0 */ 2961 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2962 reg = <0x78000 0x4>, 2963 <0x78004 0x4>; 2964 reg-names = "rev", "sysc"; 2965 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2966 <SYSC_IDLE_NO>, 2967 <SYSC_IDLE_SMART>; 2968 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2969 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2970 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2971 clock-names = "fck", "ahclkx"; 2972 #address-cells = <1>; 2973 #size-cells = <1>; 2974 ranges = <0x0 0x78000 0x2000>, 2975 <0x48450000 0x48450000 0x400000>; 2976 2977 mcasp7: mcasp@0 { 2978 compatible = "ti,dra7-mcasp-audio"; 2979 reg = <0x0 0x2000>, 2980 <0x48450000 0x1000>; /* L3 data port */ 2981 reg-names = "mpu","dat"; 2982 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2984 interrupt-names = "tx", "rx"; 2985 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 2986 dma-names = "tx", "rx"; 2987 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2988 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2989 clock-names = "fck", "ahclkx"; 2990 status = "disabled"; 2991 }; 2992 }; 2993 2994 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ 2995 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2996 reg = <0x7c000 0x4>, 2997 <0x7c004 0x4>; 2998 reg-names = "rev", "sysc"; 2999 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3000 <SYSC_IDLE_NO>, 3001 <SYSC_IDLE_SMART>; 3002 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 3003 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 3004 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 3005 clock-names = "fck", "ahclkx"; 3006 #address-cells = <1>; 3007 #size-cells = <1>; 3008 ranges = <0x0 0x7c000 0x2000>, 3009 <0x48454000 0x48454000 0x400000>; 3010 3011 mcasp8: mcasp@0 { 3012 compatible = "ti,dra7-mcasp-audio"; 3013 reg = <0x0 0x2000>, 3014 <0x48454000 0x1000>; /* L3 data port */ 3015 reg-names = "mpu","dat"; 3016 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 3017 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 3018 interrupt-names = "tx", "rx"; 3019 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 3020 dma-names = "tx", "rx"; 3021 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 3022 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 3023 clock-names = "fck", "ahclkx"; 3024 status = "disabled"; 3025 }; 3026 }; 3027 3028 target-module@80000 { /* 0x48480000, ap 31 16.0 */ 3029 compatible = "ti,sysc-omap4", "ti,sysc"; 3030 reg = <0x80020 0x4>; 3031 reg-names = "rev"; 3032 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; 3033 clock-names = "fck"; 3034 #address-cells = <1>; 3035 #size-cells = <1>; 3036 ranges = <0x0 0x80000 0x2000>; 3037 3038 dcan2: can@0 { 3039 compatible = "ti,dra7-d_can"; 3040 reg = <0x0 0x2000>; 3041 syscon-raminit = <&scm_conf 0x558 1>; 3042 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 3043 clocks = <&sys_clkin1>; 3044 status = "disabled"; 3045 }; 3046 }; 3047 3048 target-module@84000 { /* 0x48484000, ap 3 10.0 */ 3049 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 3050 reg = <0x85200 0x4>, 3051 <0x85208 0x4>, 3052 <0x85204 0x4>; 3053 reg-names = "rev", "sysc", "syss"; 3054 ti,sysc-mask = <0>; 3055 ti,sysc-midle = <SYSC_IDLE_FORCE>, 3056 <SYSC_IDLE_NO>; 3057 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3058 <SYSC_IDLE_NO>; 3059 ti,syss-mask = <1>; 3060 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; 3061 clock-names = "fck"; 3062 #address-cells = <1>; 3063 #size-cells = <1>; 3064 ranges = <0x0 0x84000 0x4000>; 3065 /* 3066 * Do not allow gating of cpsw clock as workaround 3067 * for errata i877. Keeping internal clock disabled 3068 * causes the device switching characteristics 3069 * to degrade over time and eventually fail to meet 3070 * the data manual delay time/skew specs. 3071 */ 3072 ti,no-idle; 3073 3074 mac_sw: switch@0 { 3075 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; 3076 reg = <0x0 0x4000>; 3077 ranges = <0 0 0x4000>; 3078 clocks = <&gmac_main_clk>; 3079 clock-names = "fck"; 3080 #address-cells = <1>; 3081 #size-cells = <1>; 3082 syscon = <&scm_conf>; 3083 status = "disabled"; 3084 3085 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 3089 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 3090 3091 ethernet-ports { 3092 #address-cells = <1>; 3093 #size-cells = <0>; 3094 3095 cpsw_port1: port@1 { 3096 reg = <1>; 3097 label = "port1"; 3098 mac-address = [ 00 00 00 00 00 00 ]; 3099 phys = <&phy_gmii_sel 1>; 3100 }; 3101 3102 cpsw_port2: port@2 { 3103 reg = <2>; 3104 label = "port2"; 3105 mac-address = [ 00 00 00 00 00 00 ]; 3106 phys = <&phy_gmii_sel 2>; 3107 }; 3108 }; 3109 3110 davinci_mdio_sw: mdio@1000 { 3111 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 3112 clocks = <&gmac_main_clk>; 3113 clock-names = "fck"; 3114 #address-cells = <1>; 3115 #size-cells = <0>; 3116 bus_freq = <1000000>; 3117 reg = <0x1000 0x100>; 3118 }; 3119 3120 cpts { 3121 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; 3122 clock-names = "cpts"; 3123 }; 3124 }; 3125 }; 3126 }; 3127}; 3128 3129&l4_per3 { /* 0x48800000 */ 3130 compatible = "ti,dra7-l4-per3", "simple-pm-bus"; 3131 power-domains = <&prm_l4per>; 3132 clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>; 3133 clock-names = "fck"; 3134 reg = <0x48800000 0x800>, 3135 <0x48800800 0x800>, 3136 <0x48801000 0x400>, 3137 <0x48801400 0x400>, 3138 <0x48801800 0x400>; 3139 reg-names = "ap", "la", "ia0", "ia1", "ia2"; 3140 #address-cells = <1>; 3141 #size-cells = <1>; 3142 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ 3143 3144 segment@0 { /* 0x48800000 */ 3145 compatible = "simple-pm-bus"; 3146 #address-cells = <1>; 3147 #size-cells = <1>; 3148 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 3149 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 3150 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 3151 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 3152 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 3153 <0x00020000 0x00020000 0x001000>, /* ap 5 */ 3154 <0x00021000 0x00021000 0x001000>, /* ap 6 */ 3155 <0x00022000 0x00022000 0x001000>, /* ap 7 */ 3156 <0x00023000 0x00023000 0x001000>, /* ap 8 */ 3157 <0x00024000 0x00024000 0x001000>, /* ap 9 */ 3158 <0x00025000 0x00025000 0x001000>, /* ap 10 */ 3159 <0x00026000 0x00026000 0x001000>, /* ap 11 */ 3160 <0x00027000 0x00027000 0x001000>, /* ap 12 */ 3161 <0x00028000 0x00028000 0x001000>, /* ap 13 */ 3162 <0x00029000 0x00029000 0x001000>, /* ap 14 */ 3163 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ 3164 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ 3165 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ 3166 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ 3167 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ 3168 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ 3169 <0x00170000 0x00170000 0x010000>, /* ap 21 */ 3170 <0x00180000 0x00180000 0x001000>, /* ap 22 */ 3171 <0x00190000 0x00190000 0x010000>, /* ap 23 */ 3172 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ 3173 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ 3174 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ 3175 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ 3176 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ 3177 <0x00038000 0x00038000 0x001000>, /* ap 29 */ 3178 <0x00039000 0x00039000 0x001000>, /* ap 30 */ 3179 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ 3180 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ 3181 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ 3182 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ 3183 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ 3184 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ 3185 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ 3186 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ 3187 <0x00040000 0x00040000 0x001000>, /* ap 39 */ 3188 <0x00041000 0x00041000 0x001000>, /* ap 40 */ 3189 <0x00042000 0x00042000 0x001000>, /* ap 41 */ 3190 <0x00043000 0x00043000 0x001000>, /* ap 42 */ 3191 <0x00044000 0x00044000 0x001000>, /* ap 43 */ 3192 <0x00045000 0x00045000 0x001000>, /* ap 44 */ 3193 <0x00046000 0x00046000 0x001000>, /* ap 45 */ 3194 <0x00047000 0x00047000 0x001000>, /* ap 46 */ 3195 <0x00048000 0x00048000 0x001000>, /* ap 47 */ 3196 <0x00049000 0x00049000 0x001000>, /* ap 48 */ 3197 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ 3198 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ 3199 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ 3200 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ 3201 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ 3202 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ 3203 <0x00050000 0x00050000 0x001000>, /* ap 55 */ 3204 <0x00051000 0x00051000 0x001000>, /* ap 56 */ 3205 <0x00052000 0x00052000 0x001000>, /* ap 57 */ 3206 <0x00053000 0x00053000 0x001000>, /* ap 58 */ 3207 <0x00054000 0x00054000 0x001000>, /* ap 59 */ 3208 <0x00055000 0x00055000 0x001000>, /* ap 60 */ 3209 <0x00056000 0x00056000 0x001000>, /* ap 61 */ 3210 <0x00057000 0x00057000 0x001000>, /* ap 62 */ 3211 <0x00058000 0x00058000 0x001000>, /* ap 63 */ 3212 <0x00059000 0x00059000 0x001000>, /* ap 64 */ 3213 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ 3214 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ 3215 <0x00064000 0x00064000 0x001000>, /* ap 67 */ 3216 <0x00065000 0x00065000 0x001000>, /* ap 68 */ 3217 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ 3218 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ 3219 <0x00060000 0x00060000 0x001000>, /* ap 71 */ 3220 <0x00061000 0x00061000 0x001000>, /* ap 72 */ 3221 <0x00062000 0x00062000 0x001000>, /* ap 73 */ 3222 <0x00063000 0x00063000 0x001000>, /* ap 74 */ 3223 <0x00140000 0x00140000 0x020000>, /* ap 75 */ 3224 <0x00160000 0x00160000 0x001000>, /* ap 76 */ 3225 <0x00016000 0x00016000 0x001000>, /* ap 77 */ 3226 <0x00017000 0x00017000 0x001000>, /* ap 78 */ 3227 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ 3228 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ 3229 <0x00004000 0x00004000 0x001000>, /* ap 81 */ 3230 <0x00005000 0x00005000 0x001000>, /* ap 82 */ 3231 <0x00080000 0x00080000 0x020000>, /* ap 83 */ 3232 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ 3233 <0x00100000 0x00100000 0x020000>, /* ap 85 */ 3234 <0x00120000 0x00120000 0x001000>, /* ap 86 */ 3235 <0x00010000 0x00010000 0x001000>, /* ap 87 */ 3236 <0x00011000 0x00011000 0x001000>, /* ap 88 */ 3237 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ 3238 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ 3239 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ 3240 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ 3241 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ 3242 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ 3243 <0x00002000 0x00002000 0x001000>, /* ap 95 */ 3244 <0x00003000 0x00003000 0x001000>; /* ap 96 */ 3245 3246 target-module@2000 { /* 0x48802000, ap 95 7c.0 */ 3247 compatible = "ti,sysc-omap4", "ti,sysc"; 3248 reg = <0x2000 0x4>, 3249 <0x2010 0x4>; 3250 reg-names = "rev", "sysc"; 3251 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3252 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3253 <SYSC_IDLE_NO>, 3254 <SYSC_IDLE_SMART>; 3255 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3256 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; 3257 clock-names = "fck"; 3258 #address-cells = <1>; 3259 #size-cells = <1>; 3260 ranges = <0x0 0x2000 0x1000>; 3261 3262 mailbox13: mailbox@0 { 3263 compatible = "ti,omap4-mailbox"; 3264 reg = <0x0 0x200>; 3265 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 3269 #mbox-cells = <1>; 3270 ti,mbox-num-users = <4>; 3271 ti,mbox-num-fifos = <12>; 3272 status = "disabled"; 3273 }; 3274 }; 3275 3276 target-module@4000 { /* 0x48804000, ap 81 20.0 */ 3277 compatible = "ti,sysc"; 3278 status = "disabled"; 3279 #address-cells = <1>; 3280 #size-cells = <1>; 3281 ranges = <0x0 0x4000 0x1000>; 3282 }; 3283 3284 target-module@a000 { /* 0x4880a000, ap 89 18.0 */ 3285 compatible = "ti,sysc"; 3286 status = "disabled"; 3287 #address-cells = <1>; 3288 #size-cells = <1>; 3289 ranges = <0x0 0xa000 0x1000>; 3290 }; 3291 3292 target-module@10000 { /* 0x48810000, ap 87 28.0 */ 3293 compatible = "ti,sysc"; 3294 status = "disabled"; 3295 #address-cells = <1>; 3296 #size-cells = <1>; 3297 ranges = <0x0 0x10000 0x1000>; 3298 }; 3299 3300 target-module@16000 { /* 0x48816000, ap 77 1e.0 */ 3301 compatible = "ti,sysc"; 3302 status = "disabled"; 3303 #address-cells = <1>; 3304 #size-cells = <1>; 3305 ranges = <0x0 0x16000 0x1000>; 3306 }; 3307 3308 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ 3309 compatible = "ti,sysc"; 3310 status = "disabled"; 3311 #address-cells = <1>; 3312 #size-cells = <1>; 3313 ranges = <0x0 0x1c000 0x1000>; 3314 }; 3315 3316 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ 3317 compatible = "ti,sysc"; 3318 status = "disabled"; 3319 #address-cells = <1>; 3320 #size-cells = <1>; 3321 ranges = <0x0 0x1e000 0x1000>; 3322 }; 3323 3324 target-module@20000 { /* 0x48820000, ap 5 08.0 */ 3325 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3326 reg = <0x20000 0x4>, 3327 <0x20010 0x4>; 3328 reg-names = "rev", "sysc"; 3329 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3330 SYSC_OMAP4_SOFTRESET)>; 3331 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3332 <SYSC_IDLE_NO>, 3333 <SYSC_IDLE_SMART>, 3334 <SYSC_IDLE_SMART_WKUP>; 3335 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3336 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; 3337 clock-names = "fck"; 3338 #address-cells = <1>; 3339 #size-cells = <1>; 3340 ranges = <0x0 0x20000 0x1000>; 3341 3342 timer5: timer@0 { 3343 compatible = "ti,omap5430-timer"; 3344 reg = <0x0 0x80>; 3345 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; 3346 clock-names = "fck", "timer_sys_ck"; 3347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3348 }; 3349 }; 3350 3351 target-module@22000 { /* 0x48822000, ap 7 24.0 */ 3352 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3353 reg = <0x22000 0x4>, 3354 <0x22010 0x4>; 3355 reg-names = "rev", "sysc"; 3356 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3357 SYSC_OMAP4_SOFTRESET)>; 3358 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3359 <SYSC_IDLE_NO>, 3360 <SYSC_IDLE_SMART>, 3361 <SYSC_IDLE_SMART_WKUP>; 3362 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3363 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; 3364 clock-names = "fck"; 3365 #address-cells = <1>; 3366 #size-cells = <1>; 3367 ranges = <0x0 0x22000 0x1000>; 3368 3369 timer6: timer@0 { 3370 compatible = "ti,omap5430-timer"; 3371 reg = <0x0 0x80>; 3372 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; 3373 clock-names = "fck", "timer_sys_ck"; 3374 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3375 }; 3376 }; 3377 3378 target-module@24000 { /* 0x48824000, ap 9 26.0 */ 3379 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3380 reg = <0x24000 0x4>, 3381 <0x24010 0x4>; 3382 reg-names = "rev", "sysc"; 3383 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3384 SYSC_OMAP4_SOFTRESET)>; 3385 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3386 <SYSC_IDLE_NO>, 3387 <SYSC_IDLE_SMART>, 3388 <SYSC_IDLE_SMART_WKUP>; 3389 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3390 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; 3391 clock-names = "fck"; 3392 #address-cells = <1>; 3393 #size-cells = <1>; 3394 ranges = <0x0 0x24000 0x1000>; 3395 3396 timer7: timer@0 { 3397 compatible = "ti,omap5430-timer"; 3398 reg = <0x0 0x80>; 3399 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>; 3400 clock-names = "fck", "timer_sys_ck"; 3401 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 3402 }; 3403 }; 3404 3405 target-module@26000 { /* 0x48826000, ap 11 0c.0 */ 3406 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3407 reg = <0x26000 0x4>, 3408 <0x26010 0x4>; 3409 reg-names = "rev", "sysc"; 3410 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3411 SYSC_OMAP4_SOFTRESET)>; 3412 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3413 <SYSC_IDLE_NO>, 3414 <SYSC_IDLE_SMART>, 3415 <SYSC_IDLE_SMART_WKUP>; 3416 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3417 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; 3418 clock-names = "fck"; 3419 #address-cells = <1>; 3420 #size-cells = <1>; 3421 ranges = <0x0 0x26000 0x1000>; 3422 3423 timer8: timer@0 { 3424 compatible = "ti,omap5430-timer"; 3425 reg = <0x0 0x80>; 3426 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>; 3427 clock-names = "fck", "timer_sys_ck"; 3428 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 3429 }; 3430 }; 3431 3432 target-module@28000 { /* 0x48828000, ap 13 16.0 */ 3433 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3434 reg = <0x28000 0x4>, 3435 <0x28010 0x4>; 3436 reg-names = "rev", "sysc"; 3437 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3438 SYSC_OMAP4_SOFTRESET)>; 3439 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3440 <SYSC_IDLE_NO>, 3441 <SYSC_IDLE_SMART>, 3442 <SYSC_IDLE_SMART_WKUP>; 3443 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3444 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; 3445 clock-names = "fck"; 3446 #address-cells = <1>; 3447 #size-cells = <1>; 3448 ranges = <0x0 0x28000 0x1000>; 3449 3450 timer13: timer@0 { 3451 compatible = "ti,omap5430-timer"; 3452 reg = <0x0 0x80>; 3453 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>; 3454 clock-names = "fck", "timer_sys_ck"; 3455 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 3456 ti,timer-pwm; 3457 }; 3458 }; 3459 3460 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ 3461 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3462 reg = <0x2a000 0x4>, 3463 <0x2a010 0x4>; 3464 reg-names = "rev", "sysc"; 3465 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3466 SYSC_OMAP4_SOFTRESET)>; 3467 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3468 <SYSC_IDLE_NO>, 3469 <SYSC_IDLE_SMART>, 3470 <SYSC_IDLE_SMART_WKUP>; 3471 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3472 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; 3473 clock-names = "fck"; 3474 #address-cells = <1>; 3475 #size-cells = <1>; 3476 ranges = <0x0 0x2a000 0x1000>; 3477 3478 timer14: timer@0 { 3479 compatible = "ti,omap5430-timer"; 3480 reg = <0x0 0x80>; 3481 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; 3482 clock-names = "fck", "timer_sys_ck"; 3483 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 3484 ti,timer-pwm; 3485 }; 3486 }; 3487 timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ 3488 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3489 reg = <0x2c000 0x4>, 3490 <0x2c010 0x4>; 3491 reg-names = "rev", "sysc"; 3492 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3493 SYSC_OMAP4_SOFTRESET)>; 3494 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3495 <SYSC_IDLE_NO>, 3496 <SYSC_IDLE_SMART>, 3497 <SYSC_IDLE_SMART_WKUP>; 3498 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3499 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; 3500 clock-names = "fck"; 3501 #address-cells = <1>; 3502 #size-cells = <1>; 3503 ranges = <0x0 0x2c000 0x1000>; 3504 3505 timer15: timer@0 { 3506 compatible = "ti,omap5430-timer"; 3507 reg = <0x0 0x80>; 3508 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; 3509 clock-names = "fck", "timer_sys_ck"; 3510 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 3511 ti,timer-pwm; 3512 }; 3513 }; 3514 3515 timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ 3516 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3517 reg = <0x2e000 0x4>, 3518 <0x2e010 0x4>; 3519 reg-names = "rev", "sysc"; 3520 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3521 SYSC_OMAP4_SOFTRESET)>; 3522 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3523 <SYSC_IDLE_NO>, 3524 <SYSC_IDLE_SMART>, 3525 <SYSC_IDLE_SMART_WKUP>; 3526 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3527 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; 3528 clock-names = "fck"; 3529 #address-cells = <1>; 3530 #size-cells = <1>; 3531 ranges = <0x0 0x2e000 0x1000>; 3532 3533 timer16: timer@0 { 3534 compatible = "ti,omap5430-timer"; 3535 reg = <0x0 0x80>; 3536 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; 3537 clock-names = "fck", "timer_sys_ck"; 3538 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 3539 ti,timer-pwm; 3540 }; 3541 }; 3542 3543 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ 3544 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 3545 reg = <0x38074 0x4>, 3546 <0x38078 0x4>; 3547 reg-names = "rev", "sysc"; 3548 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3549 <SYSC_IDLE_NO>, 3550 <SYSC_IDLE_SMART>, 3551 <SYSC_IDLE_SMART_WKUP>; 3552 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ 3553 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; 3554 clock-names = "fck"; 3555 #address-cells = <1>; 3556 #size-cells = <1>; 3557 ranges = <0x0 0x38000 0x1000>; 3558 3559 rtc: rtc@0 { 3560 compatible = "ti,am3352-rtc"; 3561 reg = <0x0 0x100>; 3562 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 3564 clocks = <&sys_32k_ck>; 3565 }; 3566 }; 3567 3568 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ 3569 compatible = "ti,sysc-omap4", "ti,sysc"; 3570 reg = <0x3a000 0x4>, 3571 <0x3a010 0x4>; 3572 reg-names = "rev", "sysc"; 3573 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3574 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3575 <SYSC_IDLE_NO>, 3576 <SYSC_IDLE_SMART>; 3577 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3578 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; 3579 clock-names = "fck"; 3580 #address-cells = <1>; 3581 #size-cells = <1>; 3582 ranges = <0x0 0x3a000 0x1000>; 3583 3584 mailbox2: mailbox@0 { 3585 compatible = "ti,omap4-mailbox"; 3586 reg = <0x0 0x200>; 3587 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 3591 #mbox-cells = <1>; 3592 ti,mbox-num-users = <4>; 3593 ti,mbox-num-fifos = <12>; 3594 status = "disabled"; 3595 }; 3596 }; 3597 3598 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ 3599 compatible = "ti,sysc-omap4", "ti,sysc"; 3600 reg = <0x3c000 0x4>, 3601 <0x3c010 0x4>; 3602 reg-names = "rev", "sysc"; 3603 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3604 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3605 <SYSC_IDLE_NO>, 3606 <SYSC_IDLE_SMART>; 3607 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3608 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; 3609 clock-names = "fck"; 3610 #address-cells = <1>; 3611 #size-cells = <1>; 3612 ranges = <0x0 0x3c000 0x1000>; 3613 3614 mailbox3: mailbox@0 { 3615 compatible = "ti,omap4-mailbox"; 3616 reg = <0x0 0x200>; 3617 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 3621 #mbox-cells = <1>; 3622 ti,mbox-num-users = <4>; 3623 ti,mbox-num-fifos = <12>; 3624 status = "disabled"; 3625 }; 3626 }; 3627 3628 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ 3629 compatible = "ti,sysc-omap4", "ti,sysc"; 3630 reg = <0x3e000 0x4>, 3631 <0x3e010 0x4>; 3632 reg-names = "rev", "sysc"; 3633 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3634 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3635 <SYSC_IDLE_NO>, 3636 <SYSC_IDLE_SMART>; 3637 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3638 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; 3639 clock-names = "fck"; 3640 #address-cells = <1>; 3641 #size-cells = <1>; 3642 ranges = <0x0 0x3e000 0x1000>; 3643 3644 mailbox4: mailbox@0 { 3645 compatible = "ti,omap4-mailbox"; 3646 reg = <0x0 0x200>; 3647 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 3651 #mbox-cells = <1>; 3652 ti,mbox-num-users = <4>; 3653 ti,mbox-num-fifos = <12>; 3654 status = "disabled"; 3655 }; 3656 }; 3657 3658 target-module@40000 { /* 0x48840000, ap 39 64.0 */ 3659 compatible = "ti,sysc-omap4", "ti,sysc"; 3660 reg = <0x40000 0x4>, 3661 <0x40010 0x4>; 3662 reg-names = "rev", "sysc"; 3663 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3664 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3665 <SYSC_IDLE_NO>, 3666 <SYSC_IDLE_SMART>; 3667 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3668 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; 3669 clock-names = "fck"; 3670 #address-cells = <1>; 3671 #size-cells = <1>; 3672 ranges = <0x0 0x40000 0x1000>; 3673 3674 mailbox5: mailbox@0 { 3675 compatible = "ti,omap4-mailbox"; 3676 reg = <0x0 0x200>; 3677 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 3681 #mbox-cells = <1>; 3682 ti,mbox-num-users = <4>; 3683 ti,mbox-num-fifos = <12>; 3684 status = "disabled"; 3685 }; 3686 }; 3687 3688 target-module@42000 { /* 0x48842000, ap 41 4e.0 */ 3689 compatible = "ti,sysc-omap4", "ti,sysc"; 3690 reg = <0x42000 0x4>, 3691 <0x42010 0x4>; 3692 reg-names = "rev", "sysc"; 3693 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3694 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3695 <SYSC_IDLE_NO>, 3696 <SYSC_IDLE_SMART>; 3697 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3698 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; 3699 clock-names = "fck"; 3700 #address-cells = <1>; 3701 #size-cells = <1>; 3702 ranges = <0x0 0x42000 0x1000>; 3703 3704 mailbox6: mailbox@0 { 3705 compatible = "ti,omap4-mailbox"; 3706 reg = <0x0 0x200>; 3707 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 3711 #mbox-cells = <1>; 3712 ti,mbox-num-users = <4>; 3713 ti,mbox-num-fifos = <12>; 3714 status = "disabled"; 3715 }; 3716 }; 3717 3718 target-module@44000 { /* 0x48844000, ap 43 42.0 */ 3719 compatible = "ti,sysc-omap4", "ti,sysc"; 3720 reg = <0x44000 0x4>, 3721 <0x44010 0x4>; 3722 reg-names = "rev", "sysc"; 3723 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3724 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3725 <SYSC_IDLE_NO>, 3726 <SYSC_IDLE_SMART>; 3727 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3728 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; 3729 clock-names = "fck"; 3730 #address-cells = <1>; 3731 #size-cells = <1>; 3732 ranges = <0x0 0x44000 0x1000>; 3733 3734 mailbox7: mailbox@0 { 3735 compatible = "ti,omap4-mailbox"; 3736 reg = <0x0 0x200>; 3737 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 3741 #mbox-cells = <1>; 3742 ti,mbox-num-users = <4>; 3743 ti,mbox-num-fifos = <12>; 3744 status = "disabled"; 3745 }; 3746 }; 3747 3748 target-module@46000 { /* 0x48846000, ap 45 48.0 */ 3749 compatible = "ti,sysc-omap4", "ti,sysc"; 3750 reg = <0x46000 0x4>, 3751 <0x46010 0x4>; 3752 reg-names = "rev", "sysc"; 3753 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3754 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3755 <SYSC_IDLE_NO>, 3756 <SYSC_IDLE_SMART>; 3757 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3758 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; 3759 clock-names = "fck"; 3760 #address-cells = <1>; 3761 #size-cells = <1>; 3762 ranges = <0x0 0x46000 0x1000>; 3763 3764 mailbox8: mailbox@0 { 3765 compatible = "ti,omap4-mailbox"; 3766 reg = <0x0 0x200>; 3767 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 3771 #mbox-cells = <1>; 3772 ti,mbox-num-users = <4>; 3773 ti,mbox-num-fifos = <12>; 3774 status = "disabled"; 3775 }; 3776 }; 3777 3778 target-module@48000 { /* 0x48848000, ap 47 36.0 */ 3779 compatible = "ti,sysc"; 3780 status = "disabled"; 3781 #address-cells = <1>; 3782 #size-cells = <1>; 3783 ranges = <0x0 0x48000 0x1000>; 3784 }; 3785 3786 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ 3787 compatible = "ti,sysc"; 3788 status = "disabled"; 3789 #address-cells = <1>; 3790 #size-cells = <1>; 3791 ranges = <0x0 0x4a000 0x1000>; 3792 }; 3793 3794 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ 3795 compatible = "ti,sysc"; 3796 status = "disabled"; 3797 #address-cells = <1>; 3798 #size-cells = <1>; 3799 ranges = <0x0 0x4c000 0x1000>; 3800 }; 3801 3802 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ 3803 compatible = "ti,sysc"; 3804 status = "disabled"; 3805 #address-cells = <1>; 3806 #size-cells = <1>; 3807 ranges = <0x0 0x4e000 0x1000>; 3808 }; 3809 3810 target-module@50000 { /* 0x48850000, ap 55 40.0 */ 3811 compatible = "ti,sysc"; 3812 status = "disabled"; 3813 #address-cells = <1>; 3814 #size-cells = <1>; 3815 ranges = <0x0 0x50000 0x1000>; 3816 }; 3817 3818 target-module@52000 { /* 0x48852000, ap 57 54.0 */ 3819 compatible = "ti,sysc"; 3820 status = "disabled"; 3821 #address-cells = <1>; 3822 #size-cells = <1>; 3823 ranges = <0x0 0x52000 0x1000>; 3824 }; 3825 3826 target-module@54000 { /* 0x48854000, ap 59 1a.0 */ 3827 compatible = "ti,sysc"; 3828 status = "disabled"; 3829 #address-cells = <1>; 3830 #size-cells = <1>; 3831 ranges = <0x0 0x54000 0x1000>; 3832 }; 3833 3834 target-module@56000 { /* 0x48856000, ap 61 22.0 */ 3835 compatible = "ti,sysc"; 3836 status = "disabled"; 3837 #address-cells = <1>; 3838 #size-cells = <1>; 3839 ranges = <0x0 0x56000 0x1000>; 3840 }; 3841 3842 target-module@58000 { /* 0x48858000, ap 63 2a.0 */ 3843 compatible = "ti,sysc"; 3844 status = "disabled"; 3845 #address-cells = <1>; 3846 #size-cells = <1>; 3847 ranges = <0x0 0x58000 0x1000>; 3848 }; 3849 3850 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ 3851 compatible = "ti,sysc"; 3852 status = "disabled"; 3853 #address-cells = <1>; 3854 #size-cells = <1>; 3855 ranges = <0x0 0x5a000 0x1000>; 3856 }; 3857 3858 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ 3859 compatible = "ti,sysc"; 3860 status = "disabled"; 3861 #address-cells = <1>; 3862 #size-cells = <1>; 3863 ranges = <0x0 0x5c000 0x1000>; 3864 }; 3865 3866 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ 3867 compatible = "ti,sysc-omap4", "ti,sysc"; 3868 reg = <0x5e000 0x4>, 3869 <0x5e010 0x4>; 3870 reg-names = "rev", "sysc"; 3871 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3872 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3873 <SYSC_IDLE_NO>, 3874 <SYSC_IDLE_SMART>; 3875 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3876 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; 3877 clock-names = "fck"; 3878 #address-cells = <1>; 3879 #size-cells = <1>; 3880 ranges = <0x0 0x5e000 0x1000>; 3881 3882 mailbox9: mailbox@0 { 3883 compatible = "ti,omap4-mailbox"; 3884 reg = <0x0 0x200>; 3885 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3889 #mbox-cells = <1>; 3890 ti,mbox-num-users = <4>; 3891 ti,mbox-num-fifos = <12>; 3892 status = "disabled"; 3893 }; 3894 }; 3895 3896 target-module@60000 { /* 0x48860000, ap 71 4a.0 */ 3897 compatible = "ti,sysc-omap4", "ti,sysc"; 3898 reg = <0x60000 0x4>, 3899 <0x60010 0x4>; 3900 reg-names = "rev", "sysc"; 3901 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3902 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3903 <SYSC_IDLE_NO>, 3904 <SYSC_IDLE_SMART>; 3905 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3906 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; 3907 clock-names = "fck"; 3908 #address-cells = <1>; 3909 #size-cells = <1>; 3910 ranges = <0x0 0x60000 0x1000>; 3911 3912 mailbox10: mailbox@0 { 3913 compatible = "ti,omap4-mailbox"; 3914 reg = <0x0 0x200>; 3915 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3919 #mbox-cells = <1>; 3920 ti,mbox-num-users = <4>; 3921 ti,mbox-num-fifos = <12>; 3922 status = "disabled"; 3923 }; 3924 }; 3925 3926 target-module@62000 { /* 0x48862000, ap 73 74.0 */ 3927 compatible = "ti,sysc-omap4", "ti,sysc"; 3928 reg = <0x62000 0x4>, 3929 <0x62010 0x4>; 3930 reg-names = "rev", "sysc"; 3931 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3932 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3933 <SYSC_IDLE_NO>, 3934 <SYSC_IDLE_SMART>; 3935 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3936 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; 3937 clock-names = "fck"; 3938 #address-cells = <1>; 3939 #size-cells = <1>; 3940 ranges = <0x0 0x62000 0x1000>; 3941 3942 mailbox11: mailbox@0 { 3943 compatible = "ti,omap4-mailbox"; 3944 reg = <0x0 0x200>; 3945 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 3949 #mbox-cells = <1>; 3950 ti,mbox-num-users = <4>; 3951 ti,mbox-num-fifos = <12>; 3952 status = "disabled"; 3953 }; 3954 }; 3955 3956 target-module@64000 { /* 0x48864000, ap 67 52.0 */ 3957 compatible = "ti,sysc-omap4", "ti,sysc"; 3958 reg = <0x64000 0x4>, 3959 <0x64010 0x4>; 3960 reg-names = "rev", "sysc"; 3961 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3962 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3963 <SYSC_IDLE_NO>, 3964 <SYSC_IDLE_SMART>; 3965 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3966 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; 3967 clock-names = "fck"; 3968 #address-cells = <1>; 3969 #size-cells = <1>; 3970 ranges = <0x0 0x64000 0x1000>; 3971 3972 mailbox12: mailbox@0 { 3973 compatible = "ti,omap4-mailbox"; 3974 reg = <0x0 0x200>; 3975 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 3979 #mbox-cells = <1>; 3980 ti,mbox-num-users = <4>; 3981 ti,mbox-num-fifos = <12>; 3982 status = "disabled"; 3983 }; 3984 }; 3985 3986 target-module@80000 { /* 0x48880000, ap 83 0e.1 */ 3987 compatible = "ti,sysc-omap4", "ti,sysc"; 3988 reg = <0x80000 0x4>, 3989 <0x80010 0x4>; 3990 reg-names = "rev", "sysc"; 3991 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 3992 ti,sysc-midle = <SYSC_IDLE_FORCE>, 3993 <SYSC_IDLE_NO>, 3994 <SYSC_IDLE_SMART>, 3995 <SYSC_IDLE_SMART_WKUP>; 3996 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3997 <SYSC_IDLE_NO>, 3998 <SYSC_IDLE_SMART>, 3999 <SYSC_IDLE_SMART_WKUP>; 4000 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4001 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; 4002 clock-names = "fck"; 4003 #address-cells = <1>; 4004 #size-cells = <1>; 4005 ranges = <0x0 0x80000 0x20000>; 4006 4007 omap_dwc3_1: omap_dwc3_1@0 { 4008 compatible = "ti,dwc3"; 4009 reg = <0x0 0x10000>; 4010 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4011 #address-cells = <1>; 4012 #size-cells = <1>; 4013 utmi-mode = <2>; 4014 ranges = <0 0 0x20000>; 4015 4016 usb1: usb@10000 { 4017 compatible = "snps,dwc3"; 4018 reg = <0x10000 0x17000>; 4019 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4022 interrupt-names = "peripheral", 4023 "host", 4024 "otg"; 4025 phys = <&usb2_phy1>, <&usb3_phy1>; 4026 phy-names = "usb2-phy", "usb3-phy"; 4027 maximum-speed = "super-speed"; 4028 dr_mode = "otg"; 4029 snps,dis_u3_susphy_quirk; 4030 snps,dis_u2_susphy_quirk; 4031 }; 4032 }; 4033 }; 4034 4035 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ 4036 compatible = "ti,sysc-omap4", "ti,sysc"; 4037 reg = <0xc0000 0x4>, 4038 <0xc0010 0x4>; 4039 reg-names = "rev", "sysc"; 4040 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4041 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4042 <SYSC_IDLE_NO>, 4043 <SYSC_IDLE_SMART>, 4044 <SYSC_IDLE_SMART_WKUP>; 4045 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4046 <SYSC_IDLE_NO>, 4047 <SYSC_IDLE_SMART>, 4048 <SYSC_IDLE_SMART_WKUP>; 4049 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4050 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; 4051 clock-names = "fck"; 4052 #address-cells = <1>; 4053 #size-cells = <1>; 4054 ranges = <0x0 0xc0000 0x20000>; 4055 4056 omap_dwc3_2: omap_dwc3_2@0 { 4057 compatible = "ti,dwc3"; 4058 reg = <0x0 0x10000>; 4059 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4060 #address-cells = <1>; 4061 #size-cells = <1>; 4062 utmi-mode = <2>; 4063 ranges = <0 0 0x20000>; 4064 4065 usb2: usb@10000 { 4066 compatible = "snps,dwc3"; 4067 reg = <0x10000 0x17000>; 4068 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4071 interrupt-names = "peripheral", 4072 "host", 4073 "otg"; 4074 phys = <&usb2_phy2>; 4075 phy-names = "usb2-phy"; 4076 maximum-speed = "high-speed"; 4077 dr_mode = "otg"; 4078 snps,dis_u3_susphy_quirk; 4079 snps,dis_u2_susphy_quirk; 4080 snps,dis_metastability_quirk; 4081 }; 4082 }; 4083 }; 4084 4085 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ 4086 compatible = "ti,sysc-omap4", "ti,sysc"; 4087 reg = <0x100000 0x4>, 4088 <0x100010 0x4>; 4089 reg-names = "rev", "sysc"; 4090 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4091 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4092 <SYSC_IDLE_NO>, 4093 <SYSC_IDLE_SMART>, 4094 <SYSC_IDLE_SMART_WKUP>; 4095 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4096 <SYSC_IDLE_NO>, 4097 <SYSC_IDLE_SMART>, 4098 <SYSC_IDLE_SMART_WKUP>; 4099 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4100 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; 4101 clock-names = "fck"; 4102 #address-cells = <1>; 4103 #size-cells = <1>; 4104 ranges = <0x0 0x100000 0x20000>; 4105 4106 omap_dwc3_3: omap_dwc3_3@0 { 4107 compatible = "ti,dwc3"; 4108 reg = <0x0 0x10000>; 4109 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 4110 #address-cells = <1>; 4111 #size-cells = <1>; 4112 utmi-mode = <2>; 4113 ranges = <0 0 0x20000>; 4114 status = "disabled"; 4115 4116 usb3: usb@10000 { 4117 compatible = "snps,dwc3"; 4118 reg = <0x10000 0x17000>; 4119 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 4122 interrupt-names = "peripheral", 4123 "host", 4124 "otg"; 4125 maximum-speed = "high-speed"; 4126 dr_mode = "otg"; 4127 snps,dis_u3_susphy_quirk; 4128 snps,dis_u2_susphy_quirk; 4129 }; 4130 }; 4131 }; 4132 4133 target-module@170000 { /* 0x48970000, ap 21 0a.0 */ 4134 compatible = "ti,sysc-omap4", "ti,sysc"; 4135 reg = <0x170010 0x4>; 4136 reg-names = "sysc"; 4137 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4138 <SYSC_IDLE_NO>, 4139 <SYSC_IDLE_SMART>; 4140 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4141 <SYSC_IDLE_NO>, 4142 <SYSC_IDLE_SMART>; 4143 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; 4144 clock-names = "fck"; 4145 #address-cells = <1>; 4146 #size-cells = <1>; 4147 ranges = <0x0 0x170000 0x10000>; 4148 status = "disabled"; 4149 }; 4150 4151 target-module@190000 { /* 0x48990000, ap 23 2e.0 */ 4152 compatible = "ti,sysc-omap4", "ti,sysc"; 4153 reg = <0x190010 0x4>; 4154 reg-names = "sysc"; 4155 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4156 <SYSC_IDLE_NO>, 4157 <SYSC_IDLE_SMART>; 4158 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4159 <SYSC_IDLE_NO>, 4160 <SYSC_IDLE_SMART>; 4161 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; 4162 clock-names = "fck"; 4163 #address-cells = <1>; 4164 #size-cells = <1>; 4165 ranges = <0x0 0x190000 0x10000>; 4166 status = "disabled"; 4167 }; 4168 4169 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ 4170 compatible = "ti,sysc-omap4", "ti,sysc"; 4171 reg = <0x1b0000 0x4>, 4172 <0x1b0010 0x4>; 4173 reg-names = "rev", "sysc"; 4174 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4175 <SYSC_IDLE_NO>, 4176 <SYSC_IDLE_SMART>; 4177 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4178 <SYSC_IDLE_NO>, 4179 <SYSC_IDLE_SMART>; 4180 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; 4181 clock-names = "fck"; 4182 #address-cells = <1>; 4183 #size-cells = <1>; 4184 ranges = <0x0 0x1b0000 0x10000>; 4185 status = "disabled"; 4186 }; 4187 4188 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ 4189 compatible = "ti,sysc-omap4", "ti,sysc"; 4190 reg = <0x1d0010 0x4>; 4191 reg-names = "sysc"; 4192 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4193 <SYSC_IDLE_NO>; 4194 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4195 <SYSC_IDLE_NO>, 4196 <SYSC_IDLE_SMART>; 4197 power-domains = <&prm_vpe>; 4198 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; 4199 clock-names = "fck"; 4200 #address-cells = <1>; 4201 #size-cells = <1>; 4202 ranges = <0x0 0x1d0000 0x10000>; 4203 4204 vpe: vpe@0 { 4205 compatible = "ti,dra7-vpe"; 4206 reg = <0x0000 0x120>, 4207 <0x0700 0x80>, 4208 <0x5700 0x18>, 4209 <0xd000 0x400>; 4210 reg-names = "vpe_top", 4211 "sc", 4212 "csc", 4213 "vpdma"; 4214 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 4215 }; 4216 }; 4217 }; 4218}; 4219 4220&l4_wkup { /* 0x4ae00000 */ 4221 compatible = "ti,dra7-l4-wkup", "simple-pm-bus"; 4222 power-domains = <&prm_wkupaon>; 4223 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>; 4224 clock-names = "fck"; 4225 reg = <0x4ae00000 0x800>, 4226 <0x4ae00800 0x800>, 4227 <0x4ae01000 0x1000>; 4228 reg-names = "ap", "la", "ia0"; 4229 #address-cells = <1>; 4230 #size-cells = <1>; 4231 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ 4232 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ 4233 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ 4234 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ 4235 4236 segment@0 { /* 0x4ae00000 */ 4237 compatible = "simple-pm-bus"; 4238 #address-cells = <1>; 4239 #size-cells = <1>; 4240 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 4241 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 4242 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 4243 <0x00006000 0x00006000 0x002000>, /* ap 3 */ 4244 <0x00008000 0x00008000 0x001000>, /* ap 4 */ 4245 <0x00004000 0x00004000 0x001000>, /* ap 15 */ 4246 <0x00005000 0x00005000 0x001000>, /* ap 16 */ 4247 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ 4248 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ 4249 4250 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ 4251 compatible = "ti,sysc-omap2", "ti,sysc"; 4252 reg = <0x4000 0x4>, 4253 <0x4010 0x4>; 4254 reg-names = "rev", "sysc"; 4255 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4256 <SYSC_IDLE_NO>, 4257 <SYSC_IDLE_SMART>, 4258 <SYSC_IDLE_SMART_WKUP>; 4259 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4260 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; 4261 clock-names = "fck"; 4262 #address-cells = <1>; 4263 #size-cells = <1>; 4264 ranges = <0x0 0x4000 0x1000>; 4265 4266 counter32k: counter@0 { 4267 compatible = "ti,omap-counter32k"; 4268 reg = <0x0 0x40>; 4269 }; 4270 }; 4271 4272 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ 4273 compatible = "ti,sysc-omap4", "ti,sysc"; 4274 reg = <0x6000 0x4>; 4275 reg-names = "rev"; 4276 #address-cells = <1>; 4277 #size-cells = <1>; 4278 ranges = <0x0 0x6000 0x2000>; 4279 4280 prm: prm@0 { 4281 compatible = "ti,dra7-prm", "simple-bus"; 4282 reg = <0 0x3000>; 4283 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4284 #address-cells = <1>; 4285 #size-cells = <1>; 4286 ranges = <0 0 0x3000>; 4287 4288 prm_clocks: clocks { 4289 #address-cells = <1>; 4290 #size-cells = <0>; 4291 }; 4292 4293 prm_clockdomains: clockdomains { 4294 }; 4295 }; 4296 }; 4297 4298 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ 4299 compatible = "ti,sysc-omap4", "ti,sysc"; 4300 reg = <0xc000 0x4>; 4301 reg-names = "rev"; 4302 #address-cells = <1>; 4303 #size-cells = <1>; 4304 ranges = <0x0 0xc000 0x1000>; 4305 4306 scm_wkup: scm_conf@0 { 4307 compatible = "syscon"; 4308 reg = <0 0x1000>; 4309 }; 4310 }; 4311 }; 4312 4313 segment@10000 { /* 0x4ae10000 */ 4314 compatible = "simple-pm-bus"; 4315 #address-cells = <1>; 4316 #size-cells = <1>; 4317 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ 4318 <0x00001000 0x00011000 0x001000>, /* ap 6 */ 4319 <0x00004000 0x00014000 0x001000>, /* ap 7 */ 4320 <0x00005000 0x00015000 0x001000>, /* ap 8 */ 4321 <0x00008000 0x00018000 0x001000>, /* ap 9 */ 4322 <0x00009000 0x00019000 0x001000>, /* ap 10 */ 4323 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ 4324 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ 4325 4326 target-module@0 { /* 0x4ae10000, ap 5 20.0 */ 4327 compatible = "ti,sysc-omap2", "ti,sysc"; 4328 reg = <0x0 0x4>, 4329 <0x10 0x4>, 4330 <0x114 0x4>; 4331 reg-names = "rev", "sysc", "syss"; 4332 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 4333 SYSC_OMAP2_SOFTRESET | 4334 SYSC_OMAP2_AUTOIDLE)>; 4335 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4336 <SYSC_IDLE_NO>, 4337 <SYSC_IDLE_SMART>, 4338 <SYSC_IDLE_SMART_WKUP>; 4339 ti,syss-mask = <1>; 4340 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4341 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, 4342 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; 4343 clock-names = "fck", "dbclk"; 4344 #address-cells = <1>; 4345 #size-cells = <1>; 4346 ranges = <0x0 0x0 0x1000>; 4347 4348 gpio1: gpio@0 { 4349 compatible = "ti,omap4-gpio"; 4350 reg = <0x0 0x200>; 4351 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 4352 gpio-controller; 4353 #gpio-cells = <2>; 4354 interrupt-controller; 4355 #interrupt-cells = <2>; 4356 }; 4357 }; 4358 4359 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ 4360 compatible = "ti,sysc-omap2", "ti,sysc"; 4361 reg = <0x4000 0x4>, 4362 <0x4010 0x4>, 4363 <0x4014 0x4>; 4364 reg-names = "rev", "sysc", "syss"; 4365 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 4366 SYSC_OMAP2_SOFTRESET)>; 4367 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4368 <SYSC_IDLE_NO>, 4369 <SYSC_IDLE_SMART>, 4370 <SYSC_IDLE_SMART_WKUP>; 4371 ti,syss-mask = <1>; 4372 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4373 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; 4374 clock-names = "fck"; 4375 #address-cells = <1>; 4376 #size-cells = <1>; 4377 ranges = <0x0 0x4000 0x1000>; 4378 4379 wdt2: wdt@0 { 4380 compatible = "ti,omap3-wdt"; 4381 reg = <0x0 0x80>; 4382 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 4383 }; 4384 }; 4385 4386 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ 4387 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 4388 reg = <0x8000 0x4>, 4389 <0x8010 0x4>; 4390 reg-names = "rev", "sysc"; 4391 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 4392 SYSC_OMAP4_SOFTRESET)>; 4393 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4394 <SYSC_IDLE_NO>, 4395 <SYSC_IDLE_SMART>, 4396 <SYSC_IDLE_SMART_WKUP>; 4397 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4398 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; 4399 clock-names = "fck"; 4400 #address-cells = <1>; 4401 #size-cells = <1>; 4402 ranges = <0x0 0x8000 0x1000>; 4403 4404 timer1: timer@0 { 4405 compatible = "ti,omap5430-timer"; 4406 reg = <0x0 0x80>; 4407 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; 4408 clock-names = "fck"; 4409 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4410 ti,timer-alwon; 4411 }; 4412 }; 4413 4414 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ 4415 compatible = "ti,sysc"; 4416 status = "disabled"; 4417 #address-cells = <1>; 4418 #size-cells = <1>; 4419 ranges = <0x0 0xc000 0x1000>; 4420 }; 4421 }; 4422 4423 segment@20000 { /* 0x4ae20000 */ 4424 compatible = "simple-pm-bus"; 4425 #address-cells = <1>; 4426 #size-cells = <1>; 4427 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ 4428 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ 4429 <0x00000000 0x00020000 0x001000>, /* ap 19 */ 4430 <0x00001000 0x00021000 0x001000>, /* ap 20 */ 4431 <0x00002000 0x00022000 0x001000>, /* ap 21 */ 4432 <0x00003000 0x00023000 0x001000>, /* ap 22 */ 4433 <0x00007000 0x00027000 0x000400>, /* ap 23 */ 4434 <0x00008000 0x00028000 0x000800>, /* ap 24 */ 4435 <0x00009000 0x00029000 0x000100>, /* ap 25 */ 4436 <0x00008800 0x00028800 0x000200>, /* ap 26 */ 4437 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ 4438 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ 4439 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ 4440 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ 4441 4442 target-module@0 { /* 0x4ae20000, ap 19 08.0 */ 4443 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 4444 reg = <0x0 0x4>, 4445 <0x10 0x4>; 4446 reg-names = "rev", "sysc"; 4447 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 4448 SYSC_OMAP4_SOFTRESET)>; 4449 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4450 <SYSC_IDLE_NO>, 4451 <SYSC_IDLE_SMART>, 4452 <SYSC_IDLE_SMART_WKUP>; 4453 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4454 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; 4455 clock-names = "fck"; 4456 #address-cells = <1>; 4457 #size-cells = <1>; 4458 ranges = <0x0 0x0 0x1000>; 4459 4460 timer12: timer@0 { 4461 compatible = "ti,omap5430-timer"; 4462 reg = <0x0 0x80>; 4463 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 4464 ti,timer-alwon; 4465 ti,timer-secure; 4466 }; 4467 }; 4468 4469 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ 4470 compatible = "ti,sysc"; 4471 status = "disabled"; 4472 #address-cells = <1>; 4473 #size-cells = <1>; 4474 ranges = <0x0 0x2000 0x1000>; 4475 }; 4476 4477 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ 4478 compatible = "ti,sysc"; 4479 status = "disabled"; 4480 #address-cells = <1>; 4481 #size-cells = <1>; 4482 ranges = <0x00000000 0x00006000 0x00001000>, 4483 <0x00001000 0x00007000 0x00000400>, 4484 <0x00002000 0x00008000 0x00000800>, 4485 <0x00002800 0x00008800 0x00000200>, 4486 <0x00002a00 0x00008a00 0x00000100>, 4487 <0x00003000 0x00009000 0x00000100>; 4488 }; 4489 4490 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ 4491 compatible = "ti,sysc-omap2", "ti,sysc"; 4492 reg = <0xb050 0x4>, 4493 <0xb054 0x4>, 4494 <0xb058 0x4>; 4495 reg-names = "rev", "sysc", "syss"; 4496 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 4497 SYSC_OMAP2_SOFTRESET | 4498 SYSC_OMAP2_AUTOIDLE)>; 4499 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4500 <SYSC_IDLE_NO>, 4501 <SYSC_IDLE_SMART>, 4502 <SYSC_IDLE_SMART_WKUP>; 4503 ti,syss-mask = <1>; 4504 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4505 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; 4506 clock-names = "fck"; 4507 #address-cells = <1>; 4508 #size-cells = <1>; 4509 ranges = <0x0 0xb000 0x1000>; 4510 4511 uart10: serial@0 { 4512 compatible = "ti,dra742-uart"; 4513 reg = <0x0 0x100>; 4514 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 4515 clock-frequency = <48000000>; 4516 status = "disabled"; 4517 }; 4518 }; 4519 4520 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ 4521 compatible = "ti,sysc"; 4522 status = "disabled"; 4523 #address-cells = <1>; 4524 #size-cells = <1>; 4525 ranges = <0x0 0xf000 0x1000>; 4526 }; 4527 }; 4528 4529 segment@30000 { /* 0x4ae30000 */ 4530 compatible = "simple-pm-bus"; 4531 #address-cells = <1>; 4532 #size-cells = <1>; 4533 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ 4534 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ 4535 <0x00000000 0x00030000 0x001000>, /* ap 33 */ 4536 <0x00001000 0x00031000 0x001000>, /* ap 34 */ 4537 <0x00002000 0x00032000 0x001000>, /* ap 35 */ 4538 <0x00003000 0x00033000 0x001000>, /* ap 36 */ 4539 <0x00004000 0x00034000 0x001000>, /* ap 37 */ 4540 <0x00005000 0x00035000 0x001000>, /* ap 38 */ 4541 <0x00006000 0x00036000 0x001000>, /* ap 39 */ 4542 <0x00007000 0x00037000 0x001000>, /* ap 40 */ 4543 <0x00008000 0x00038000 0x001000>, /* ap 41 */ 4544 <0x00009000 0x00039000 0x001000>, /* ap 42 */ 4545 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ 4546 4547 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ 4548 compatible = "ti,sysc"; 4549 status = "disabled"; 4550 #address-cells = <1>; 4551 #size-cells = <1>; 4552 ranges = <0x0 0x1000 0x1000>; 4553 }; 4554 4555 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ 4556 compatible = "ti,sysc"; 4557 status = "disabled"; 4558 #address-cells = <1>; 4559 #size-cells = <1>; 4560 ranges = <0x0 0x3000 0x1000>; 4561 }; 4562 4563 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ 4564 compatible = "ti,sysc"; 4565 status = "disabled"; 4566 #address-cells = <1>; 4567 #size-cells = <1>; 4568 ranges = <0x0 0x5000 0x1000>; 4569 }; 4570 4571 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ 4572 compatible = "ti,sysc"; 4573 status = "disabled"; 4574 #address-cells = <1>; 4575 #size-cells = <1>; 4576 ranges = <0x0 0x7000 0x1000>; 4577 }; 4578 4579 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ 4580 compatible = "ti,sysc"; 4581 status = "disabled"; 4582 #address-cells = <1>; 4583 #size-cells = <1>; 4584 ranges = <0x0 0x9000 0x1000>; 4585 }; 4586 4587 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ 4588 compatible = "ti,sysc-omap4", "ti,sysc"; 4589 reg = <0xc020 0x4>; 4590 reg-names = "rev"; 4591 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; 4592 clock-names = "fck"; 4593 #address-cells = <1>; 4594 #size-cells = <1>; 4595 ranges = <0x0 0xc000 0x2000>; 4596 4597 dcan1: can@0 { 4598 compatible = "ti,dra7-d_can"; 4599 reg = <0x0 0x2000>; 4600 syscon-raminit = <&scm_conf 0x558 0>; 4601 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 4602 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; 4603 status = "disabled"; 4604 }; 4605 }; 4606 }; 4607}; 4608 4609