1 #ifndef CPER_SECTION_PCIE_H 2 #define CPER_SECTION_PCIE_H 3 4 #ifdef __cplusplus 5 extern "C" { 6 #endif 7 8 #include <stdio.h> 9 #include <json.h> 10 #include <libcper/Cper.h> 11 12 #define PCIE_ERROR_VALID_BITFIELD_NAMES \ 13 (const char *[]){ "portTypeValid", \ 14 "versionValid", \ 15 "commandStatusValid", \ 16 "deviceIDValid", \ 17 "deviceSerialNumberValid", \ 18 "bridgeControlStatusValid", \ 19 "capabilityStructureStatusValid", \ 20 "aerInfoValid" } 21 #define PCIE_ERROR_PORT_TYPES_KEYS (int[]){ 0, 1, 4, 5, 6, 7, 8, 9, 10 } 22 #define PCIE_ERROR_PORT_TYPES_VALUES \ 23 (const char *[]){ "PCI Express End Point", \ 24 "Legacy PCI End Point Device", \ 25 "Root Port", \ 26 "Upstream Switch Port", \ 27 "Downstream Switch Port", \ 28 "PCI Express to PCI/PCI-X Bridge", \ 29 "PCI/PCI-X Bridge to PCI Express Bridge", \ 30 "Root Complex Integrated Endpoint Device", \ 31 "Root Complex Event Collector" } 32 33 struct class_code { 34 UINT8 base; 35 UINT8 sub; 36 UINT8 programming; 37 const char *name; 38 }; 39 40 json_object *cper_section_pcie_to_ir(const UINT8 *section, UINT32 size, 41 char **desc_string); 42 void ir_section_pcie_to_cper(json_object *section, FILE *out); 43 44 /* 45 * This file is designed as a standard c header file and as a script friendly 46 * source fo the PCIe PCIe Capability and Advanced Error Registers structures. 47 * The template of each register is: 48 * 49 * 50 * * <Name of Capabaility Structure> 51 * * CAPABILITY_ID = <id of capability structure> 52 * * <Register Name> 53 * * Offset: <offset of the register in the capability structure> 54 * struct { 55 * <register width> <field name> : <field width>; 56 * <register width> <field name> : <field width>; 57 * <register width> <field name> : <field width>; 58 * } 59 */ 60 61 /* 62 * PCI Express Capability Structure 63 * CAPABILITY_ID = 0x10 64 * PCI Express Capability Structure Header 65 * Offset: 0x0 66 */ 67 typedef struct { 68 UINT16 capability_id : 8; // bits [7:0] - Capability ID (should be 0x10) 69 UINT16 next_capability_pointer : 8; // bits [7:0] - Next capability pointer 70 } __attribute__((packed)) pcie_capability_header_t; 71 72 /* 73 * PCI Express Capability Structure 74 * CAPABILITY_ID = 0x10 75 * PCI Express Capabilities Register 76 * Offset: 0x2 77 */ 78 typedef struct { 79 UINT16 capability_version : 4; // bits [3:0] 80 UINT16 device_port_type : 4; // bits [7:4] 81 UINT16 slot_implemented : 1; // bit [8] 82 UINT16 interrupt_message_number : 5; // bits [13:9] 83 UINT16 undefined : 1; // bit [14] 84 UINT16 flit_mode_supported : 1; // bit [15] 85 } __attribute__((packed)) pcie_capabilities_t; 86 87 static const char *device_port_type_dict[] = { 88 "PCIE", // 0x0 89 "PCI", // 0x1 90 "ROOT_PORT", // 0x4 91 "UPSTREAM", // 0x5 92 "DOWNSTREAM", // 0x6 93 "PCIE_PCI_BRIDGE", // 0x7 94 "PCI_PCIE_BRIDGE", // 0x8 95 "RCiEP", // 0x9 96 "RCEC", // 0xa 97 }; 98 99 static const size_t device_port_type_dict_size = 100 sizeof(device_port_type_dict) / sizeof(device_port_type_dict[0]); 101 102 /* 103 * Begin Of PCIe Capability Registers 104 */ 105 106 /* 107 * PCI Express Capability Structure 108 * CAPABILITY_ID = 0x10 109 * Device Capabilities Register 110 * Offset: 0x4 111 */ 112 typedef struct { 113 UINT32 max_payload_size_supported : 3; // bits [2:0] 114 UINT32 phantom_functions_supported : 2; // bits [4:3] 115 UINT32 extended_tag_field_supported : 1; // bit [5] 116 UINT32 endpoint_l0s_acceptable_latency : 3; // bits [8:6] 117 UINT32 endpoint_l1_acceptable_latency : 3; // bits [11:9] 118 UINT32 undefined : 3; // bits [14:12] 119 UINT32 role_based_error_reporting : 1; // bit [15] 120 UINT32 err_cor_subclass_capable : 1; // bit [16] 121 UINT32 rx_mps_fixed : 1; // bits [17] 122 UINT32 captured_slot_power_limit_value : 8; // bits [25:18] 123 UINT32 captured_slot_power_limit_scale : 2; // bits [27:26] 124 UINT32 function_level_reset_capability : 1; // bit [28] 125 UINT32 mixed_mps_supported : 1; // bit [29] 126 UINT32 tee_io_supported : 1; // bit [30] 127 UINT32 rsvdp : 1; // bit [31] 128 } __attribute__((packed)) device_capabilities_t; 129 130 /* 131 * PCI Express Capability Structure 132 * CAPABILITY_ID = 0x10 133 * Device Control Register 134 * Offset: 0x8 135 */ 136 typedef struct { 137 UINT16 correctable_error_reporting_enable : 1; // bit [0] 138 UINT16 non_fatal_error_reporting_enable : 1; // bit [1] 139 UINT16 fatal_error_reporting_enable : 1; // bit [2] 140 UINT16 unsupported_request_reporting_enable : 1; // bit [3] 141 UINT16 enable_relaxed_ordering : 1; // bit [4] 142 UINT16 max_payload_size : 3; // bits [7:5] 143 UINT16 extended_tag_field_enable : 1; // bit [8] 144 UINT16 phantom_functions_enable : 1; // bit [9] 145 UINT16 aux_power_pm_enable : 1; // bit [10] 146 UINT16 enable_no_snoop : 1; // bit [11] 147 UINT16 max_read_request_size : 3; // bits [14:12] 148 UINT16 function_level_reset : 1; // bit [15] 149 } __attribute__((packed)) device_control_t; 150 151 /* 152 * PCI Express Capability Structure 153 * CAPABILITY_ID = 0x10 154 * Device Status Register 155 * Offset: 0xA 156 */ 157 typedef struct { 158 UINT16 correctable_error_detected : 1; // bit [0] 159 UINT16 non_fatal_error_detected : 1; // bit [1] 160 UINT16 fatal_error_detected : 1; // bit [2] 161 UINT16 unsupported_request_detected : 1; // bit [3] 162 UINT16 aux_power_detected : 1; // bit [4] 163 UINT16 transactions_pending : 1; // bit [5] 164 UINT16 emergency_power_reduction : 2; // bits [7:6] (PCIe 4.0+) 165 UINT16 rsvdz : 8; // bits [15:8] 166 } __attribute__((packed)) device_status_t; 167 168 /* 169 * PCI Express Capability Structure 170 * CAPABILITY_ID = 0x10 171 * Link Capabilities Register 172 * Offset: 0xC 173 */ 174 typedef struct { 175 UINT32 max_link_speed : 4; // bits [3:0] 176 UINT32 maximum_link_width : 6; // bits [9:4] 177 UINT32 aspm_support : 2; // bits [11:10] 178 UINT32 l0s_exit_latency : 3; // bits [14:12] 179 UINT32 l1_exit_latency : 3; // bits [17:15] 180 UINT32 clock_power_management : 1; // bit [18] 181 UINT32 surprise_down_error_reporting_capable : 1; // bit [19] 182 UINT32 data_link_layer_link_active_reporting_capable : 1; // bit [20] 183 UINT32 link_bandwidth_notification_capability : 1; // bit [21] 184 UINT32 aspm_optionality_compliance : 1; // bit [22] 185 UINT32 rsvdp : 1; // bit [23] 186 UINT32 port_number : 8; // bits [31:24] 187 } __attribute__((packed)) link_capabilities_t; 188 189 /* 190 * PCI Express Capability Structure 191 * CAPABILITY_ID = 0x10 192 * Link Control Register 193 * Offset: 0x10 194 */ 195 typedef struct { 196 UINT16 aspm_control : 2; // bits [1:0] 197 // ptm_propagation_delay_adaptation_interpretation_bit 198 UINT16 ptm_prop_delay_adaptation_interpretation : 1; // bit [2] 199 UINT16 read_completion_boundary : 1; // bit [3] 200 UINT16 link_disable : 1; // bit [4] 201 UINT16 retrain_link : 1; // bit [5] 202 UINT16 common_clock_configuration : 1; // bit [6] 203 UINT16 extended_synch : 1; // bit [7] 204 UINT16 enable_clock_power_management : 1; // bit [8] 205 UINT16 hardware_autonomous_width_disable : 1; // bit [9] 206 UINT16 link_bandwidth_management_interrupt_enable : 1; // bit [10] 207 UINT16 link_autonomous_bandwidth_interrupt_enable : 1; // bit [11] 208 UINT16 sris_clocking : 1; // bit [12] 209 UINT16 flit_mode_disable : 1; // bit [13] 210 UINT16 drs_signaling_control : 1; // bits [15:14] 211 } __attribute__((packed)) link_control_t; 212 213 /* 214 * PCI Express Capability Structure 215 * CAPABILITY_ID = 0x10 216 * Link Status Register 217 * Offset: 0x12 218 */ 219 typedef struct { 220 UINT16 current_link_speed : 4; // bits [3:0] 221 UINT16 negotiated_link_width : 6; // bits [9:4] 222 UINT16 undefined : 1; // bit [10] 223 UINT16 link_training : 1; // bit [11] 224 UINT16 slot_clock_configuration : 1; // bit [12] 225 UINT16 data_link_layer_link_active : 1; // bit [13] 226 UINT16 link_bandwidth_management_status : 1; // bit [14] 227 UINT16 link_autonomous_bandwidth_status : 1; // bit [15] 228 } __attribute__((packed)) link_status_t; 229 230 /* 231 * PCI Express Capability Structure 232 * CAPABILITY_ID = 0x10 233 * Slot Capabilities Register 234 * Offset: 0x14 235 */ 236 typedef struct { 237 UINT32 attention_button_present : 1; // bit [0] 238 UINT32 power_controller_present : 1; // bit [1] 239 UINT32 mrl_sensor_present : 1; // bit [2] 240 UINT32 attention_indicator_present : 1; // bit [3] 241 UINT32 power_indicator_present : 1; // bit [4] 242 UINT32 hot_plug_surprise : 1; // bit [5] 243 UINT32 hot_plug_capable : 1; // bit [6] 244 UINT32 slot_power_limit_value : 8; // bits [14:7] 245 UINT32 slot_power_limit_scale : 2; // bits [16:15] 246 UINT32 electromechanical_interlock_present : 1; // bit [17] 247 UINT32 no_command_completed_support : 1; // bit [18] 248 UINT32 physical_slot_number : 13; // bits [31:19] 249 } __attribute__((packed)) slot_capabilities_t; 250 251 /* 252 * PCI Express Capability Structure 253 * CAPABILITY_ID = 0x10 254 * Slot Control Register 255 * Offset: 0x18 256 */ 257 typedef struct { 258 UINT16 attention_button_pressed_enable : 1; // bit [0] 259 UINT16 power_fault_detected_enable : 1; // bit [1] 260 UINT16 mrl_sensor_changed_enable : 1; // bit [2] 261 UINT16 presence_detect_changed_enable : 1; // bit [3] 262 UINT16 command_completed_interrupt_enable : 1; // bit [4] 263 UINT16 hot_plug_interrupt_enable : 1; // bit [5] 264 UINT16 attention_indicator_control : 2; // bits [7:6] 265 UINT16 power_indicator_control : 2; // bits [9:8] 266 UINT16 power_controller_control : 1; // bit [10] 267 UINT16 electromechanical_interlock_control : 1; // bit [11] 268 UINT16 data_link_layer_state_changed_enable : 1; // bit [12] 269 UINT16 auto_slot_power_limit_disable : 1; // bit [13] 270 UINT16 in_band_pd_disable : 1; // bit [14] 271 UINT16 rsvdp : 1; // bit [15] 272 } __attribute__((packed)) slot_control_t; 273 274 /* 275 * PCI Express Capability Structure 276 * CAPABILITY_ID = 0x10 277 * Slot Status Register 278 * Offset: 0x1A 279 */ 280 typedef struct { 281 UINT16 attention_button_pressed : 1; // bit [0] 282 UINT16 power_fault_detected : 1; // bit [1] 283 UINT16 mrl_sensor_changed : 1; // bit [2] 284 UINT16 presence_detect_changed : 1; // bit [3] 285 UINT16 command_completed : 1; // bit [4] 286 UINT16 mrl_sensor_state : 1; // bit [5] 287 UINT16 presence_detect_state : 1; // bit [6] 288 UINT16 electromechanical_interlock_status : 1; // bit [7] 289 UINT16 data_link_layer_state_changed : 1; // bit [8] 290 UINT16 rsvdz : 7; // bits [15:9] 291 } __attribute__((packed)) slot_status_t; 292 293 /* 294 * PCI Express Capability Structure 295 * CAPABILITY_ID = 0x10 296 * Root Control Register 297 * Offset: 0x1C 298 */ 299 typedef struct { 300 UINT16 system_error_on_correctable_error_enable : 1; // bit [0] 301 UINT16 system_error_on_non_fatal_error_enable : 1; // bit [1] 302 UINT16 system_error_on_fatal_error_enable : 1; // bit [2] 303 UINT16 pme_interrupt_enable : 1; // bit [3] 304 UINT16 configuration_rrs_software_visibility_enable : 1; // bit [4] 305 UINT16 no_nfm_subtree_below_this_root_port : 1; // bit [5] 306 UINT16 rsvdp : 10; // bits [15:6] 307 } __attribute__((packed)) root_control_t; 308 309 /* 310 * PCI Express Capability Structure 311 * CAPABILITY_ID = 0x10 312 * Root Capabilities Register 313 * Offset: 0x1E 314 */ 315 typedef struct { 316 UINT16 configuraton_rrs_software_visibility : 1; // bit [0] 317 UINT16 rsvdp : 15; // bits [15:1] 318 } __attribute__((packed)) root_capabilities_t; 319 320 /* 321 * PCI Express Capability Structure 322 * CAPABILITY_ID = 0x10 323 * Root Status Register 324 * Offset: 0x20 325 */ 326 typedef struct { 327 UINT32 pme_requester_id : 16; // bits [15:0] 328 UINT32 pme_status : 1; // bit [16] 329 UINT32 pme_pending : 1; // bit [17] 330 UINT32 rsvdp : 14; // bits [31:18] 331 } __attribute__((packed)) root_status_t; 332 333 /* 334 * PCI Express Capability Structure 335 * CAPABILITY_ID = 0x10 336 * Device Capabilities 2 Register 337 * Offset: 0x24 338 */ 339 typedef struct { 340 UINT32 completion_timeout_ranges_supported : 4; // bits [3:0] 341 UINT32 completion_timeout_disable_supported : 1; // bit [4] 342 UINT32 ari_forwarding_supported : 1; // bit [5] 343 UINT32 atomic_op_routing_supported : 1; // bit [6] 344 UINT32 _32_bit_atomicop_completer_supported : 1; // bit [7] 345 UINT32 _64_bit_atomicop_completer_supported : 1; // bit [8] 346 UINT32 _128_bit_cas_completer_supported : 1; // bit [9] 347 UINT32 no_ro_enabled_pr_pr_passing : 1; // bit [10] 348 UINT32 ltr_mechanism_supported : 1; // bit [11] 349 UINT32 tph_completer_supported : 2; // bits [13:12] 350 UINT32 undefined : 2; // bit [15:14] 351 UINT32 _10_bit_tag_completer_supported : 1; // bit [16] 352 UINT32 _10_bit_tag_requester_supported : 1; // bit [17] 353 UINT32 obff_supported : 2; // bits [19:18] 354 UINT32 extended_fmt_field_supported : 1; // bit [20] 355 UINT32 end_end_tlp_prefix_supported : 1; // bit [21] 356 UINT32 max_end_end_tlp_prefixes : 2; // bits [23:22] 357 UINT32 emergency_power_reduction_supported : 2; // bits [25:24] 358 // emergency_power_reduction_initialization_required 359 UINT32 emergency_power_reduction_init_required : 1; // bit [26] 360 UINT32 rsvdp : 1; // bit [27] 361 UINT32 dmwr_completer_supported : 1; // bit [28] 362 UINT32 dmwr_lengths_supported : 2; // bits [30:29] 363 UINT32 frs_supported : 1; // bit [31] 364 } __attribute__((packed)) device_capabilities2_t; 365 366 /* 367 * PCI Express Capability Structure 368 * CAPABILITY_ID = 0x10 369 * Device Control 2 Register 370 * Offset: 0x28 371 */ 372 typedef struct { 373 UINT16 completion_timeout_value : 4; // bits [3:0] 374 UINT16 completion_timeout_disable : 1; // bit [4] 375 UINT16 ari_forwarding_enable : 1; // bit [5] 376 UINT16 atomicop_requester_enable : 1; // bit [6] 377 UINT16 atomicop_egress_blocking : 1; // bit [7] 378 UINT16 ido_request_enable : 1; // bit [8] 379 UINT16 ido_completion_enable : 1; // bit [9] 380 UINT16 ltr_mechanism_enable : 1; // bit [10] 381 UINT16 emergency_power_reduction_request : 1; // bit [11] 382 UINT16 bit_tag_requester_10_enable : 1; // bit [12] 383 UINT16 obff_enable : 2; // bits [14:13] 384 UINT16 end_end_tlp_prefix_blocking : 1; // bit [15] 385 } __attribute__((packed)) device_control2_t; 386 387 /* 388 * PCI Express Capability Structure 389 * CAPABILITY_ID = 0x10 390 * Device Status 2 Register 391 * Offset: 0x2A 392 */ 393 typedef struct { 394 UINT16 rsvdz : 16; // bits [15:0] 395 } __attribute__((packed)) device_status2_t; 396 397 /* 398 * PCI Express Capability Structure 399 * CAPABILITY_ID = 0x10 400 * Link Capabilities 2 Register 401 * Offset: 0x2C 402 */ 403 typedef struct { 404 UINT32 rsvdp : 1; // bit [0] 405 union { 406 struct { 407 UINT32 l_2_5g_supported : 1; 408 UINT32 l_5g_supported : 1; 409 UINT32 l_8g_supported : 1; 410 UINT32 l_16g_supported : 1; 411 UINT32 l_32g_supported : 1; 412 UINT32 reserved1 : 1; 413 UINT32 reserved2 : 1; 414 } __attribute__((packed)) supported_link_speeds; 415 UINT32 supported_link_speeds_register : 7; // bits [7:1] 416 }; 417 418 UINT32 crosslink_supported : 1; // bit [8] 419 UINT32 lower_skp_os_generation_supported : 7; // bit [15:9] 420 UINT32 lower_skp_os_reception_supported : 7; // bit [22:16] 421 UINT32 retimer_presence_detect_supported : 1; // bit [23] 422 UINT32 two_retimers_presence_detect_supported : 1; // bit [24] 423 UINT32 reserved : 6; // bits [30:25] 424 UINT32 drs_supported : 1; // bit [31] 425 } __attribute__((packed)) link_capabilities2_t; 426 427 /* 428 * PCI Express Capability Structure 429 * CAPABILITY_ID = 0x10 430 * Link Control 2 Register 431 * Offset: 0x30 432 */ 433 typedef struct { 434 UINT16 target_link_speed : 4; // bits [3:0] 435 UINT16 enter_compliance : 1; // bit [4] 436 UINT16 hardware_autonomous_speed_disable : 1; // bit [5] 437 UINT16 selectable_de_emphasis : 1; // bit [6] 438 UINT16 transmit_margin : 3; // bits [9:7] 439 UINT16 enter_modified_compliance : 1; // bit [10] 440 UINT16 compliance_sos : 1; // bit [11] 441 UINT16 compliance_preset_de_emphasis : 4; // bits [15:12] 442 } __attribute__((packed)) link_control2_t; 443 444 /* 445 * PCI Express Capability Structure 446 * CAPABILITY_ID = 0x10 447 * Link Status 2 Register 448 * Offset: 0x32 449 */ 450 typedef struct { 451 UINT16 current_de_emphasis_level : 1; // bit [0] 452 UINT16 equalization_8gts_complete : 1; // bit [1] 453 UINT16 equalization_8gts_phase1_successful : 1; // bit [2] 454 UINT16 equalization_8gts_phase2_successful : 1; // bit [3] 455 UINT16 equalization_8gts_phase3_successful : 1; // bit [4] 456 UINT16 link_equalization_request_8gts : 1; // bit [5] 457 UINT16 retimer_presence_detected : 1; // bit [6] 458 UINT16 two_retimers_presence_detected : 1; // bit [7] 459 UINT16 crosslink_resolution : 2; // bits [9:8] 460 UINT16 flit_mode_status : 1; // bit [10] 461 UINT16 rsvdz : 1; // bit [11] 462 UINT16 downstream_component_presence : 3; // bits [14:12] 463 UINT16 drs_message_received : 1; // bit [15] 464 } __attribute__((packed)) link_status2_t; 465 466 /* 467 * PCI Express Capability Structure 468 * CAPABILITY_ID = 0x10 469 * Slot Capabilities 2 Register 470 * Offset: 0x34 471 */ 472 typedef struct { 473 UINT32 rsvdp : 32; // bits [31:0] 474 } __attribute__((packed)) slot_capabilities2_t; 475 476 /* 477 * PCI Express Capability Structure 478 * CAPABILITY_ID = 0x10 479 * Slot Control 2 Register 480 * Offset: 0x38 481 */ 482 typedef struct { 483 UINT16 rsvdp : 16; // bits [15:0] 484 } __attribute__((packed)) slot_control2_t; 485 486 /* 487 * PCI Express Capability Structure 488 * CAPABILITY_ID = 0x10 489 * Slot Status 2 Register 490 * Offset: 0x3A 491 */ 492 typedef struct { 493 UINT16 rsvdp : 16; // bits [15:0] 494 } __attribute__((packed)) slot_status2_t; 495 496 /* 497 * End Of PCIe Capability Registers 498 */ 499 500 /* 501 * Begin Of AER Registers 502 */ 503 504 /* 505 * PCI Express Advanced Error Reporting Capability Structure 506 * CAPABILITY_ID = 0x01 507 * AER Capability Header 508 * Offset: 0x0 509 */ 510 typedef struct { 511 UINT16 capability_id : 16; // bits [15:0] 512 UINT16 capability_version : 4; // bits [19:16] 513 UINT16 next_capability_offset : 12; // bits [31:20] 514 } __attribute__((packed)) capability_header_t; 515 516 /* 517 * PCI Express Advanced Error Reporting Capability Structure 518 * CAPABILITY_ID = 0x01 519 * Uncorrectable Error Status Register 520 * Offset: 0x4 521 */ 522 typedef struct { 523 UINT32 undefined : 1; // bits [0] 524 UINT32 rsvdz1 : 3; // bits [3:1] 525 UINT32 data_link_protocol_error_status : 1; // bit [4] 526 UINT32 surprise_down_error_status : 1; // bit [5] 527 UINT32 rsvdz2 : 6; // bits [11:6] 528 UINT32 poisoned_tlp_received : 1; // bit [12] 529 UINT32 flow_control_protocol_error_status : 1; // bit [13] 530 UINT32 completion_timeout_status : 1; // bit [14] 531 UINT32 completer_abort_status : 1; // bit [15] 532 UINT32 unexpected_completion_status : 1; // bit [16] 533 UINT32 receiver_overflow_status : 1; // bit [17] 534 UINT32 malformed_tlp_status : 1; // bit [18] 535 UINT32 ecrc_error_status : 1; // bit [19] 536 UINT32 unsupported_request_error_status : 1; // bit [20] 537 UINT32 acs_violation_status : 1; // bit [21] 538 UINT32 uncorrectable_internal_error_status : 1; // bit [22] 539 UINT32 mc_blocked_tlp_status : 1; // bit [23] 540 UINT32 atomicop_egress_blocked_status : 1; // bit [24] 541 UINT32 tlp_prefix_blocked_error_status : 1; // bit [25] 542 UINT32 poisoned_tlp_egress_blocked_status : 1; // bit [26] 543 UINT32 dmwr_request_egress_blocked_status : 1; // bit [27] 544 UINT32 ide_check_failed_status : 1; // bit [28] 545 UINT32 misrouted_ide_tlp_status : 1; // bit [29] 546 UINT32 pcrc_check_failed_status : 1; // bit [30] 547 UINT32 tlp_translation_egress_blocked_status : 1; // bit [31] 548 } __attribute__((packed)) uncorrectable_error_status_t; 549 550 /* 551 * PCI Express Advanced Error Reporting Capability Structure 552 * CAPABILITY_ID = 0x01 553 * Uncorrectable Error Mask Register 554 * Offset: 0x8 555 */ 556 typedef struct { 557 UINT32 undefined : 1; // bits [0] 558 UINT32 rsvdz1 : 3; // bits [3:1] 559 UINT32 data_link_protocol_error_mask : 1; // bit [4] 560 UINT32 surprise_down_error_mask : 1; // bit [5] 561 UINT32 rsvdz2 : 6; // bits [11:6] 562 UINT32 poisoned_tlp_received_mask : 1; // bit [12] 563 UINT32 flow_control_protocol_error_mask : 1; // bit [13] 564 UINT32 completion_timeout_mask : 1; // bit [14] 565 UINT32 completer_abort_mask : 1; // bit [15] 566 UINT32 unexpected_completion_mask : 1; // bit [16] 567 UINT32 receiver_overflow_mask : 1; // bit [17] 568 UINT32 malformed_tlp_mask : 1; // bit [18] 569 UINT32 ecrc_error_mask : 1; // bit [19] 570 UINT32 unsupported_request_error_mask : 1; // bit [20] 571 UINT32 acs_violation_mask : 1; // bit [21] 572 UINT32 uncorrectable_internal_error_mask : 1; // bit [22] 573 UINT32 mc_blocked_tlp_mask : 1; // bit [23] 574 UINT32 atomicop_egress_blocked_mask : 1; // bit [24] 575 UINT32 tlp_prefix_blocked_error_mask : 1; // bit [25] 576 UINT32 poisoned_tlp_egress_blocked_mask : 1; // bit [26] 577 UINT32 dmwr_request_egress_blocked_mask : 1; // bit [27] 578 UINT32 ide_check_failed_mask : 1; // bit [28] 579 UINT32 misrouted_ide_tlp_mask : 1; // bit [29] 580 UINT32 pcrc_check_failed_mask : 1; // bit [30] 581 UINT32 tlp_translation_egress_blocked_mask : 1; // bit [31] 582 } __attribute__((packed)) uncorrectable_error_mask_t; 583 584 static const char *severity_dict[] = { 585 "NonFatal", // 0x0 586 "Fatal", // 0x1 587 }; 588 589 static const size_t severity_dict_size = 590 sizeof(severity_dict) / sizeof(severity_dict[0]); 591 592 static const char *supported_dict[] = { 593 "NotSupported", // 0x0 594 "Supported", // 0x1 595 }; 596 597 static const size_t supported_dict_size = 598 sizeof(severity_dict) / sizeof(severity_dict[0]); 599 600 static const char *enabled_dict[] = { 601 "Disabled", // 0x0 602 "Enabled", // 0x1 603 }; 604 605 static const size_t enabled_dict_size = 606 sizeof(enabled_dict) / sizeof(enabled_dict[0]); 607 608 static const char *passing_dict[] = { 609 "Failed", // 0x0 610 "Passing", // 0x1 611 }; 612 613 static const size_t passing_dict_size = 614 sizeof(passing_dict) / sizeof(passing_dict[0]); 615 616 /* 617 * PCI Express Advanced Error Reporting Capability Structure 618 * CAPABILITY_ID = 0x01 619 * Uncorrectable Error Severity Register 620 * Offset: 0xC 621 */ 622 typedef struct { 623 UINT32 undefined : 1; // bits [0] 624 UINT32 rsvdz1 : 3; // bits [3:1] 625 UINT32 data_link_protocol_error_severity : 1; // bit [4] 626 UINT32 surprise_down_error_severity : 1; // bit [5] 627 UINT32 rsvdz2 : 6; // bits [11:6] 628 UINT32 poisoned_tlp_received_severity : 1; // bit [12] 629 UINT32 flow_control_protocol_error_severity : 1; // bit [13] 630 UINT32 completion_timeout_severity : 1; // bit [14] 631 UINT32 completer_abort_severity : 1; // bit [15] 632 UINT32 unexpected_completion_severity : 1; // bit [16] 633 UINT32 receiver_overflow_severity : 1; // bit [17] 634 UINT32 malformed_tlp_severity : 1; // bit [18] 635 UINT32 ecrc_error_severity : 1; // bit [19] 636 UINT32 unsupported_request_error_severity : 1; // bit [20] 637 UINT32 acs_violation_severity : 1; // bit [21] 638 UINT32 uncorrectable_internal_error_severity : 1; // bit [22] 639 UINT32 mc_blocked_tlp_severity : 1; // bit [23] 640 UINT32 atomicop_egress_blocked_severity : 1; // bit [24] 641 UINT32 tlp_prefix_blocked_error_severity : 1; // bit [25] 642 UINT32 poisoned_tlp_egress_blocked_severity : 1; // bit [26] 643 UINT32 dmwr_request_egress_blocked_severity : 1; // bit [27] 644 UINT32 ide_check_failed_severity : 1; // bit [28] 645 UINT32 misrouted_ide_tlp_severity : 1; // bit [29] 646 UINT32 pcrc_check_failed_severity : 1; // bit [30] 647 UINT32 tlp_translation_egress_blocked_severity : 1; // bit [31] 648 } __attribute__((packed)) uncorrectable_error_severity_t; 649 650 /* 651 * PCI Express Advanced Error Reporting Capability Structure 652 * CAPABILITY_ID = 0x01 653 * Correctable Error Status Register 654 * Offset: 0x10 655 */ 656 typedef struct { 657 UINT32 receiver_error_status : 1; // bit [0] 658 UINT32 rsvdz1 : 5; // bits [5:1] 659 UINT32 bad_tlp_status : 1; // bit [6] 660 UINT32 bad_dllp_status : 1; // bit [7] 661 UINT32 replay_num_rollover_status : 1; // bit [8] 662 UINT32 rsvdz2 : 3; // bits [11:9] 663 UINT32 replay_timer_timeout_status : 1; // bit [12] 664 UINT32 advisory_non_fatal_error_status : 1; // bit [13] 665 UINT32 corrected_internal_error_status : 1; // bit [14] 666 UINT32 header_log_overflow_status : 1; // bit [15] 667 UINT32 rsvdz3 : 16; // bits [31:16] 668 } __attribute__((packed)) correctable_error_status_t; 669 670 /* 671 * PCI Express Advanced Error Reporting Capability Structure 672 * CAPABILITY_ID = 0x01 673 * Correctable Error Mask Register 674 * Offset: 0x14 675 */ 676 typedef struct { 677 UINT32 receiver_error_mask : 1; // bit [0] 678 UINT32 rsvdz1 : 5; // bits [5:1] 679 UINT32 bad_tlp_mask : 1; // bit [6] 680 UINT32 bad_dllp_mask : 1; // bit [7] 681 UINT32 replay_num_rollover_mask : 1; // bit [8] 682 UINT32 rsvdz2 : 3; // bits [11:9] 683 UINT32 replay_timer_timeout_mask : 1; // bit [12] 684 UINT32 advisory_non_fatal_error_mask : 1; // bit [13] 685 UINT32 corrected_internal_error_mask : 1; // bit [14] 686 UINT32 header_log_overflow_mask : 1; // bit [15] 687 UINT32 rsvdz3 : 16; // bits [31:16] 688 } __attribute__((packed)) correctable_error_mask_t; 689 690 /* 691 * PCI Express Advanced Error Reporting Capability Structure 692 * CAPABILITY_ID = 0x01 693 * Advanced Error Capabilities and Control Register 694 * Offset: 0x18 695 */ 696 typedef struct { 697 UINT32 first_error_pointer : 5; // bits [4:0] 698 UINT32 ecrc_generation_capable : 1; // bit [5] 699 UINT32 ecrc_generation_enable : 1; // bit [6] 700 UINT32 ecrc_check_capable : 1; // bit [7] 701 UINT32 ecrc_check_enable : 1; // bit [8] 702 UINT32 multiple_header_recording_capable : 1; // bit [9] 703 UINT32 multiple_header_recording_enable : 1; // bit [10] 704 UINT32 tlp_prefix_log_present : 1; // bit [11] 705 UINT32 completion_timeout_prefix_header_log_capable : 1; // bit [12] 706 UINT32 header_log_size : 5; // bits [17:13] 707 UINT32 logged_tlp_was_flit_mode : 1; // bit [18] 708 UINT32 logged_tlp_size : 5; // bits [23:19] 709 UINT32 rsvdp : 8; // bits [31:24] 710 } __attribute__((packed)) advanced_error_capabilities_and_control_t; 711 712 /* 713 * PCI Express Advanced Error Reporting Capability Structure 714 * CAPABILITY_ID = 0x01 715 * Root Error Command Register 716 * Offset: 0x2C 717 */ 718 typedef struct { 719 UINT32 correctable_error_reporting_enable : 1; // bit [0] 720 UINT32 non_fatal_error_reporting_enable : 1; // bit [1] 721 UINT32 fatal_error_reporting_enable : 1; // bit [2] 722 UINT32 rsvdp : 29; // bits [31:3] 723 } __attribute__((packed)) root_error_command_t; 724 725 /* 726 * PCI Express Advanced Error Reporting Capability Structure 727 * CAPABILITY_ID = 0x01 728 * Root Error Status Register 729 * Offset: 0x30 730 */ 731 typedef struct { 732 UINT32 err_cor_received : 1; // bit [0] 733 UINT32 multiple_err_cor_received : 1; // bit [1] 734 UINT32 err_fatal_nonfatal_received : 1; // bit [2] 735 UINT32 multiple_err_fatal_nonfatal_received : 1; // bit [3] 736 UINT32 first_uncorrectable_fatal : 1; // bit [4] 737 UINT32 non_fatal_error_messages_received : 1; // bit [5] 738 UINT32 fatal_error_messages_received : 1; // bit [6] 739 UINT32 err_cor_subclass : 2; // bit [8:7] 740 UINT32 rsvdz : 16; // bit [9:26] 741 UINT32 advanced_error_interrupt_message_number : 5; // bits [31:27] 742 } __attribute__((packed)) root_error_status_t; 743 744 /* 745 * PCI Express Advanced Error Reporting Capability Structure 746 * CAPABILITY_ID = 0x01 747 * Error Source Identification Register 748 * Offset: 0x34 749 */ 750 typedef struct { 751 UINT32 err_cor_source_identification : 16; // bits [15:0] 752 UINT32 err_fatal_nonfatal_source_identification : 16; // bits [31:16] 753 } __attribute__((packed)) error_source_id_t; 754 755 typedef struct { 756 pcie_capability_header_t pcie_capability_header; 757 pcie_capabilities_t pcie_capabilities; 758 device_capabilities_t device_capabilities; 759 device_control_t device_control; 760 device_status_t device_status; 761 link_capabilities_t link_capabilities; 762 link_control_t link_control; 763 link_status_t link_status; 764 slot_capabilities_t slot_capabilities; 765 slot_control_t slot_control; 766 slot_status_t slot_status; 767 root_control_t root_control; 768 root_capabilities_t root_capabilities; 769 root_status_t root_status; 770 // "2" postfixed only valid when pcie_capabilities_fields.cap_version >= 2 771 device_capabilities2_t device_capabilities2; 772 device_control2_t device_control2; 773 device_status2_t device_status2; 774 link_capabilities2_t link_capabilities2; 775 link_control2_t link_control2; 776 link_status2_t link_status2; 777 slot_capabilities2_t slot_capabilities2; 778 slot_control2_t slot_control2; 779 slot_status2_t slot_status2; 780 } __attribute__((packed)) capability_registers; 781 782 typedef struct { 783 capability_header_t capability_header; 784 uncorrectable_error_status_t uncorrectable_error_status; 785 uncorrectable_error_mask_t uncorrectable_error_mask; 786 uncorrectable_error_severity_t uncorrectable_error_severity; 787 correctable_error_status_t correctable_error_status; 788 correctable_error_mask_t correctable_error_mask; 789 advanced_error_capabilities_and_control_t 790 advanced_error_capabilities_and_control; 791 UINT32 tlp_header[4]; 792 root_error_command_t root_error_command; 793 root_error_status_t root_error_status; 794 error_source_id_t error_source_id; 795 union { 796 struct { // Non-flit mode TLP prefix logs 797 UINT32 log[4]; 798 } non_flit_logs; 799 struct { // Flit mode TLP header logs 800 UINT32 header[10]; 801 } flit_tlp_header_logs; 802 } tlp_pfrefix; 803 } __attribute__((packed)) aer_info_registers; 804 805 #ifdef __cplusplus 806 } 807 #endif 808 809 #endif 810