1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <miiphy.h>
9 #include <netdev.h>
10 #include <asm/io.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13
14 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
15 #include <../serdes/a38x/high_speed_env_spec.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /*
20 * Those values and defines are taken from the Marvell U-Boot version
21 * "u-boot-2013.01-15t1-clearfog"
22 */
23 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff
24 #define BOARD_GPP_OUT_ENA_MID 0xffffffff
25
26 #define BOARD_GPP_OUT_VAL_LOW 0x0
27 #define BOARD_GPP_OUT_VAL_MID 0x0
28 #define BOARD_GPP_POL_LOW 0x0
29 #define BOARD_GPP_POL_MID 0x0
30
31 static struct serdes_map board_serdes_map[] = {
32 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
33 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
34 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
35 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
36 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
37 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
38 };
39
hws_board_topology_load(struct serdes_map ** serdes_map_array,u8 * count)40 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
41 {
42 *serdes_map_array = board_serdes_map;
43 *count = ARRAY_SIZE(board_serdes_map);
44 return 0;
45 }
46
47 /*
48 * Define the DDR layout / topology here in the board file. This will
49 * be used by the DDR3 init code in the SPL U-Boot version to configure
50 * the DDR3 controller.
51 */
52 static struct mv_ddr_topology_map board_topology_map = {
53 DEBUG_LEVEL_ERROR,
54 0x1, /* active interfaces */
55 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
56 { { { {0x1, 0, 0, 0},
57 {0x1, 0, 0, 0},
58 {0x1, 0, 0, 0},
59 {0x1, 0, 0, 0},
60 {0x1, 0, 0, 0} },
61 SPEED_BIN_DDR_1600K, /* speed_bin */
62 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
63 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
64 MV_DDR_FREQ_800, /* frequency */
65 0, 0, /* cas_wl cas_l */
66 MV_DDR_TEMP_LOW, /* temperature */
67 MV_DDR_TIM_DEFAULT} }, /* timing */
68 BUS_MASK_32BIT, /* Busses mask */
69 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
70 { {0} }, /* raw spd data */
71 {0} /* timing parameters */
72 };
73
mv_ddr_topology_map_get(void)74 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
75 {
76 /* Return the board topology as defined in the board code */
77 return &board_topology_map;
78 }
79
board_early_init_f(void)80 int board_early_init_f(void)
81 {
82 /* Configure MPP */
83 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
84 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
85 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
86 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
87 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
88 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
89 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
90 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
91
92 /* Set GPP Out value */
93 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
94 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
95
96 /* Set GPP Polarity */
97 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
98 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
99
100 /* Set GPP Out Enable */
101 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
102 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
103
104 return 0;
105 }
106
board_init(void)107 int board_init(void)
108 {
109 /* Address of boot parameters */
110 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
111
112 /* Toggle GPIO41 to reset onboard switch and phy */
113 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
114 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
115 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
116 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
117 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
118 mdelay(1);
119 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
120 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
121 mdelay(10);
122
123 return 0;
124 }
125
checkboard(void)126 int checkboard(void)
127 {
128 puts("Board: SolidRun ClearFog\n");
129
130 return 0;
131 }
132
board_eth_init(bd_t * bis)133 int board_eth_init(bd_t *bis)
134 {
135 cpu_eth_init(bis); /* Built in controller(s) come first */
136 return pci_eth_init(bis);
137 }
138