1 /*
2 * ASPEED INTC Controller
3 *
4 * Copyright (C) 2024 ASPEED Technology Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #include "qemu/osdep.h"
10 #include "hw/intc/aspeed_intc.h"
11 #include "hw/irq.h"
12 #include "qemu/log.h"
13 #include "trace.h"
14 #include "hw/registerfields.h"
15 #include "qapi/error.h"
16
17 /*
18 * INTC Registers
19 *
20 * values below are offset by - 0x1000 from datasheet
21 * because its memory region is start at 0x1000
22 *
23 */
24 REG32(GICINT128_EN, 0x000)
25 REG32(GICINT128_STATUS, 0x004)
26 REG32(GICINT129_EN, 0x100)
27 REG32(GICINT129_STATUS, 0x104)
28 REG32(GICINT130_EN, 0x200)
29 REG32(GICINT130_STATUS, 0x204)
30 REG32(GICINT131_EN, 0x300)
31 REG32(GICINT131_STATUS, 0x304)
32 REG32(GICINT132_EN, 0x400)
33 REG32(GICINT132_STATUS, 0x404)
34 REG32(GICINT133_EN, 0x500)
35 REG32(GICINT133_STATUS, 0x504)
36 REG32(GICINT134_EN, 0x600)
37 REG32(GICINT134_STATUS, 0x604)
38 REG32(GICINT135_EN, 0x700)
39 REG32(GICINT135_STATUS, 0x704)
40 REG32(GICINT136_EN, 0x800)
41 REG32(GICINT136_STATUS, 0x804)
42 REG32(GICINT192_201_EN, 0xB00)
43 REG32(GICINT192_201_STATUS, 0xB04)
44
45 /*
46 * INTCIO Registers
47 *
48 * values below are offset by - 0x100 from datasheet
49 * because its memory region is start at 0x100
50 *
51 */
52 REG32(GICINT192_EN, 0x00)
53 REG32(GICINT192_STATUS, 0x04)
54 REG32(GICINT193_EN, 0x10)
55 REG32(GICINT193_STATUS, 0x14)
56 REG32(GICINT194_EN, 0x20)
57 REG32(GICINT194_STATUS, 0x24)
58 REG32(GICINT195_EN, 0x30)
59 REG32(GICINT195_STATUS, 0x34)
60 REG32(GICINT196_EN, 0x40)
61 REG32(GICINT196_STATUS, 0x44)
62 REG32(GICINT197_EN, 0x50)
63 REG32(GICINT197_STATUS, 0x54)
64
65 /*
66 * SSP INTC Registers
67 */
68 REG32(SSPINT128_EN, 0x2000)
69 REG32(SSPINT128_STATUS, 0x2004)
70 REG32(SSPINT129_EN, 0x2100)
71 REG32(SSPINT129_STATUS, 0x2104)
72 REG32(SSPINT130_EN, 0x2200)
73 REG32(SSPINT130_STATUS, 0x2204)
74 REG32(SSPINT131_EN, 0x2300)
75 REG32(SSPINT131_STATUS, 0x2304)
76 REG32(SSPINT132_EN, 0x2400)
77 REG32(SSPINT132_STATUS, 0x2404)
78 REG32(SSPINT133_EN, 0x2500)
79 REG32(SSPINT133_STATUS, 0x2504)
80 REG32(SSPINT134_EN, 0x2600)
81 REG32(SSPINT134_STATUS, 0x2604)
82 REG32(SSPINT135_EN, 0x2700)
83 REG32(SSPINT135_STATUS, 0x2704)
84 REG32(SSPINT136_EN, 0x2800)
85 REG32(SSPINT136_STATUS, 0x2804)
86 REG32(SSPINT137_EN, 0x2900)
87 REG32(SSPINT137_STATUS, 0x2904)
88 REG32(SSPINT138_EN, 0x2A00)
89 REG32(SSPINT138_STATUS, 0x2A04)
90 REG32(SSPINT160_169_EN, 0x2B00)
91 REG32(SSPINT160_169_STATUS, 0x2B04)
92
93 /*
94 * SSP INTCIO Registers
95 */
96 REG32(SSPINT160_EN, 0x180)
97 REG32(SSPINT160_STATUS, 0x184)
98 REG32(SSPINT161_EN, 0x190)
99 REG32(SSPINT161_STATUS, 0x194)
100 REG32(SSPINT162_EN, 0x1A0)
101 REG32(SSPINT162_STATUS, 0x1A4)
102 REG32(SSPINT163_EN, 0x1B0)
103 REG32(SSPINT163_STATUS, 0x1B4)
104 REG32(SSPINT164_EN, 0x1C0)
105 REG32(SSPINT164_STATUS, 0x1C4)
106 REG32(SSPINT165_EN, 0x1D0)
107 REG32(SSPINT165_STATUS, 0x1D4)
108
109 /*
110 * TSP INTC Registers
111 */
112 REG32(TSPINT128_EN, 0x3000)
113 REG32(TSPINT128_STATUS, 0x3004)
114 REG32(TSPINT129_EN, 0x3100)
115 REG32(TSPINT129_STATUS, 0x3104)
116 REG32(TSPINT130_EN, 0x3200)
117 REG32(TSPINT130_STATUS, 0x3204)
118 REG32(TSPINT131_EN, 0x3300)
119 REG32(TSPINT131_STATUS, 0x3304)
120 REG32(TSPINT132_EN, 0x3400)
121 REG32(TSPINT132_STATUS, 0x3404)
122 REG32(TSPINT133_EN, 0x3500)
123 REG32(TSPINT133_STATUS, 0x3504)
124 REG32(TSPINT134_EN, 0x3600)
125 REG32(TSPINT134_STATUS, 0x3604)
126 REG32(TSPINT135_EN, 0x3700)
127 REG32(TSPINT135_STATUS, 0x3704)
128 REG32(TSPINT136_EN, 0x3800)
129 REG32(TSPINT136_STATUS, 0x3804)
130 REG32(TSPINT137_EN, 0x3900)
131 REG32(TSPINT137_STATUS, 0x3904)
132 REG32(TSPINT138_EN, 0x3A00)
133 REG32(TSPINT138_STATUS, 0x3A04)
134 REG32(TSPINT160_169_EN, 0x3B00)
135 REG32(TSPINT160_169_STATUS, 0x3B04)
136
137 /*
138 * TSP INTCIO Registers
139 */
140
141 REG32(TSPINT160_EN, 0x200)
142 REG32(TSPINT160_STATUS, 0x204)
143 REG32(TSPINT161_EN, 0x210)
144 REG32(TSPINT161_STATUS, 0x214)
145 REG32(TSPINT162_EN, 0x220)
146 REG32(TSPINT162_STATUS, 0x224)
147 REG32(TSPINT163_EN, 0x230)
148 REG32(TSPINT163_STATUS, 0x234)
149 REG32(TSPINT164_EN, 0x240)
150 REG32(TSPINT164_STATUS, 0x244)
151 REG32(TSPINT165_EN, 0x250)
152 REG32(TSPINT165_STATUS, 0x254)
153
aspeed_intc_get_irq(AspeedINTCClass * aic,uint32_t reg)154 static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
155 uint32_t reg)
156 {
157 int i;
158
159 for (i = 0; i < aic->irq_table_count; i++) {
160 if (aic->irq_table[i].enable_reg == reg ||
161 aic->irq_table[i].status_reg == reg) {
162 return &aic->irq_table[i];
163 }
164 }
165
166 /*
167 * Invalid reg.
168 */
169 g_assert_not_reached();
170 }
171
172 /*
173 * Update the state of an interrupt controller pin by setting
174 * the specified output pin to the given level.
175 * The input pin index should be between 0 and the number of input pins.
176 * The output pin index should be between 0 and the number of output pins.
177 */
aspeed_intc_update(AspeedINTCState * s,int inpin_idx,int outpin_idx,int level)178 static void aspeed_intc_update(AspeedINTCState *s, int inpin_idx,
179 int outpin_idx, int level)
180 {
181 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
182 const char *name = object_get_typename(OBJECT(s));
183
184 assert((outpin_idx < aic->num_outpins) && (inpin_idx < aic->num_inpins));
185
186 trace_aspeed_intc_update_irq(name, inpin_idx, outpin_idx, level);
187 qemu_set_irq(s->output_pins[outpin_idx], level);
188 }
189
aspeed_intc_set_irq_handler(AspeedINTCState * s,const AspeedINTCIRQ * intc_irq,uint32_t select)190 static void aspeed_intc_set_irq_handler(AspeedINTCState *s,
191 const AspeedINTCIRQ *intc_irq,
192 uint32_t select)
193 {
194 const char *name = object_get_typename(OBJECT(s));
195 uint32_t status_reg;
196 int outpin_idx;
197 int inpin_idx;
198
199 status_reg = intc_irq->status_reg;
200 outpin_idx = intc_irq->outpin_idx;
201 inpin_idx = intc_irq->inpin_idx;
202
203 if ((s->mask[inpin_idx] & select) || (s->regs[status_reg] & select)) {
204 /*
205 * a. mask is not 0 means in ISR mode
206 * sources interrupt routine are executing.
207 * b. status register value is not 0 means previous
208 * source interrupt does not be executed, yet.
209 *
210 * save source interrupt to pending variable.
211 */
212 s->pending[inpin_idx] |= select;
213 trace_aspeed_intc_pending_irq(name, inpin_idx, s->pending[inpin_idx]);
214 } else {
215 /*
216 * notify firmware which source interrupt are coming
217 * by setting status register
218 */
219 s->regs[status_reg] = select;
220 trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx,
221 s->regs[status_reg]);
222 aspeed_intc_update(s, inpin_idx, outpin_idx, 1);
223 }
224 }
225
aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState * s,const AspeedINTCIRQ * intc_irq,uint32_t select)226 static void aspeed_intc_set_irq_handler_multi_outpins(AspeedINTCState *s,
227 const AspeedINTCIRQ *intc_irq, uint32_t select)
228 {
229 const char *name = object_get_typename(OBJECT(s));
230 uint32_t status_reg;
231 int num_outpins;
232 int outpin_idx;
233 int inpin_idx;
234 int i;
235
236 num_outpins = intc_irq->num_outpins;
237 status_reg = intc_irq->status_reg;
238 outpin_idx = intc_irq->outpin_idx;
239 inpin_idx = intc_irq->inpin_idx;
240
241 for (i = 0; i < num_outpins; i++) {
242 if (select & BIT(i)) {
243 if (s->mask[inpin_idx] & BIT(i) ||
244 s->regs[status_reg] & BIT(i)) {
245 /*
246 * a. mask bit is not 0 means in ISR mode sources interrupt
247 * routine are executing.
248 * b. status bit is not 0 means previous source interrupt
249 * does not be executed, yet.
250 *
251 * save source interrupt to pending bit.
252 */
253 s->pending[inpin_idx] |= BIT(i);
254 trace_aspeed_intc_pending_irq(name, inpin_idx,
255 s->pending[inpin_idx]);
256 } else {
257 /*
258 * notify firmware which source interrupt are coming
259 * by setting status bit
260 */
261 s->regs[status_reg] |= BIT(i);
262 trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx + i,
263 s->regs[status_reg]);
264 aspeed_intc_update(s, inpin_idx, outpin_idx + i, 1);
265 }
266 }
267 }
268 }
269
270 /*
271 * GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9.
272 * GICINT128 to GICINT136 map 1:1 to input IRQs 1 to 9 and output
273 * IRQs 10 to 18. The value of input IRQ should be between 0 and
274 * the number of input pins.
275 */
aspeed_intc_set_irq(void * opaque,int irq,int level)276 static void aspeed_intc_set_irq(void *opaque, int irq, int level)
277 {
278 AspeedINTCState *s = (AspeedINTCState *)opaque;
279 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
280 const char *name = object_get_typename(OBJECT(s));
281 const AspeedINTCIRQ *intc_irq;
282 uint32_t select = 0;
283 uint32_t enable;
284 int num_outpins;
285 int inpin_idx;
286 int i;
287
288 assert(irq < aic->num_inpins);
289
290 intc_irq = &aic->irq_table[irq];
291 num_outpins = intc_irq->num_outpins;
292 inpin_idx = intc_irq->inpin_idx;
293 trace_aspeed_intc_set_irq(name, inpin_idx, level);
294 enable = s->enable[inpin_idx];
295
296 if (!level) {
297 return;
298 }
299
300 for (i = 0; i < aic->num_lines; i++) {
301 if (s->orgates[inpin_idx].levels[i]) {
302 if (enable & BIT(i)) {
303 select |= BIT(i);
304 }
305 }
306 }
307
308 if (!select) {
309 return;
310 }
311
312 trace_aspeed_intc_select(name, select);
313 if (num_outpins > 1) {
314 aspeed_intc_set_irq_handler_multi_outpins(s, intc_irq, select);
315 } else {
316 aspeed_intc_set_irq_handler(s, intc_irq, select);
317 }
318 }
319
aspeed_intc_enable_handler(AspeedINTCState * s,hwaddr offset,uint64_t data)320 static void aspeed_intc_enable_handler(AspeedINTCState *s, hwaddr offset,
321 uint64_t data)
322 {
323 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
324 const char *name = object_get_typename(OBJECT(s));
325 const AspeedINTCIRQ *intc_irq;
326 uint32_t reg = offset >> 2;
327 uint32_t old_enable;
328 uint32_t change;
329 int inpin_idx;
330
331 intc_irq = aspeed_intc_get_irq(aic, reg);
332 inpin_idx = intc_irq->inpin_idx;
333
334 assert(inpin_idx < aic->num_inpins);
335
336 /*
337 * The enable registers are used to enable source interrupts.
338 * They also handle masking and unmasking of source interrupts
339 * during the execution of the source ISR.
340 */
341
342 /* disable all source interrupt */
343 if (!data && !s->enable[inpin_idx]) {
344 s->regs[reg] = data;
345 return;
346 }
347
348 old_enable = s->enable[inpin_idx];
349 s->enable[inpin_idx] |= data;
350
351 /* enable new source interrupt */
352 if (old_enable != s->enable[inpin_idx]) {
353 trace_aspeed_intc_enable(name, s->enable[inpin_idx]);
354 s->regs[reg] = data;
355 return;
356 }
357
358 /* mask and unmask source interrupt */
359 change = s->regs[reg] ^ data;
360 if (change & data) {
361 s->mask[inpin_idx] &= ~change;
362 trace_aspeed_intc_unmask(name, change, s->mask[inpin_idx]);
363 } else {
364 s->mask[inpin_idx] |= change;
365 trace_aspeed_intc_mask(name, change, s->mask[inpin_idx]);
366 }
367
368 s->regs[reg] = data;
369 }
370
aspeed_intc_status_handler(AspeedINTCState * s,hwaddr offset,uint64_t data)371 static void aspeed_intc_status_handler(AspeedINTCState *s, hwaddr offset,
372 uint64_t data)
373 {
374 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
375 const char *name = object_get_typename(OBJECT(s));
376 const AspeedINTCIRQ *intc_irq;
377 uint32_t reg = offset >> 2;
378 int outpin_idx;
379 int inpin_idx;
380
381 if (!data) {
382 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
383 return;
384 }
385
386 intc_irq = aspeed_intc_get_irq(aic, reg);
387 outpin_idx = intc_irq->outpin_idx;
388 inpin_idx = intc_irq->inpin_idx;
389
390 assert(inpin_idx < aic->num_inpins);
391
392 /* clear status */
393 s->regs[reg] &= ~data;
394
395 /*
396 * These status registers are used for notify sources ISR are executed.
397 * If one source ISR is executed, it will clear one bit.
398 * If it clear all bits, it means to initialize this register status
399 * rather than sources ISR are executed.
400 */
401 if (data == 0xffffffff) {
402 return;
403 }
404
405 /* All source ISR execution are done */
406 if (!s->regs[reg]) {
407 trace_aspeed_intc_all_isr_done(name, inpin_idx);
408 if (s->pending[inpin_idx]) {
409 /*
410 * handle pending source interrupt
411 * notify firmware which source interrupt are pending
412 * by setting status register
413 */
414 s->regs[reg] = s->pending[inpin_idx];
415 s->pending[inpin_idx] = 0;
416 trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx,
417 s->regs[reg]);
418 aspeed_intc_update(s, inpin_idx, outpin_idx, 1);
419 } else {
420 /* clear irq */
421 trace_aspeed_intc_clear_irq(name, inpin_idx, outpin_idx, 0);
422 aspeed_intc_update(s, inpin_idx, outpin_idx, 0);
423 }
424 }
425 }
426
aspeed_intc_status_handler_multi_outpins(AspeedINTCState * s,hwaddr offset,uint64_t data)427 static void aspeed_intc_status_handler_multi_outpins(AspeedINTCState *s,
428 hwaddr offset, uint64_t data)
429 {
430 const char *name = object_get_typename(OBJECT(s));
431 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
432 const AspeedINTCIRQ *intc_irq;
433 uint32_t reg = offset >> 2;
434 int num_outpins;
435 int outpin_idx;
436 int inpin_idx;
437 int i;
438
439 if (!data) {
440 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid data 0\n", __func__);
441 return;
442 }
443
444 intc_irq = aspeed_intc_get_irq(aic, reg);
445 num_outpins = intc_irq->num_outpins;
446 outpin_idx = intc_irq->outpin_idx;
447 inpin_idx = intc_irq->inpin_idx;
448 assert(inpin_idx < aic->num_inpins);
449
450 /* clear status */
451 s->regs[reg] &= ~data;
452
453 /*
454 * The status registers are used for notify sources ISR are executed.
455 * If one source ISR is executed, it will clear one bit.
456 * If it clear all bits, it means to initialize this register status
457 * rather than sources ISR are executed.
458 */
459 if (data == 0xffffffff) {
460 return;
461 }
462
463 for (i = 0; i < num_outpins; i++) {
464 /* All source ISR executions are done from a specific bit */
465 if (data & BIT(i)) {
466 trace_aspeed_intc_all_isr_done_bit(name, inpin_idx, i);
467 if (s->pending[inpin_idx] & BIT(i)) {
468 /*
469 * Handle pending source interrupt.
470 * Notify firmware which source interrupt is pending
471 * by setting the status bit.
472 */
473 s->regs[reg] |= BIT(i);
474 s->pending[inpin_idx] &= ~BIT(i);
475 trace_aspeed_intc_trigger_irq(name, inpin_idx, outpin_idx + i,
476 s->regs[reg]);
477 aspeed_intc_update(s, inpin_idx, outpin_idx + i, 1);
478 } else {
479 /* clear irq for the specific bit */
480 trace_aspeed_intc_clear_irq(name, inpin_idx, outpin_idx + i, 0);
481 aspeed_intc_update(s, inpin_idx, outpin_idx + i, 0);
482 }
483 }
484 }
485 }
486
aspeed_intc_read(void * opaque,hwaddr offset,unsigned int size)487 static uint64_t aspeed_intc_read(void *opaque, hwaddr offset, unsigned int size)
488 {
489 AspeedINTCState *s = ASPEED_INTC(opaque);
490 const char *name = object_get_typename(OBJECT(s));
491 uint32_t reg = offset >> 2;
492 uint32_t value = 0;
493
494 value = s->regs[reg];
495 trace_aspeed_intc_read(name, offset, size, value);
496
497 return value;
498 }
499
aspeed_intc_write(void * opaque,hwaddr offset,uint64_t data,unsigned size)500 static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
501 unsigned size)
502 {
503 AspeedINTCState *s = ASPEED_INTC(opaque);
504 const char *name = object_get_typename(OBJECT(s));
505 uint32_t reg = offset >> 2;
506
507 trace_aspeed_intc_write(name, offset, size, data);
508
509 switch (reg) {
510 case R_GICINT128_EN:
511 case R_GICINT129_EN:
512 case R_GICINT130_EN:
513 case R_GICINT131_EN:
514 case R_GICINT132_EN:
515 case R_GICINT133_EN:
516 case R_GICINT134_EN:
517 case R_GICINT135_EN:
518 case R_GICINT136_EN:
519 case R_GICINT192_201_EN:
520 aspeed_intc_enable_handler(s, offset, data);
521 break;
522 case R_GICINT128_STATUS:
523 case R_GICINT129_STATUS:
524 case R_GICINT130_STATUS:
525 case R_GICINT131_STATUS:
526 case R_GICINT132_STATUS:
527 case R_GICINT133_STATUS:
528 case R_GICINT134_STATUS:
529 case R_GICINT135_STATUS:
530 case R_GICINT136_STATUS:
531 aspeed_intc_status_handler(s, offset, data);
532 break;
533 case R_GICINT192_201_STATUS:
534 aspeed_intc_status_handler_multi_outpins(s, offset, data);
535 break;
536 default:
537 s->regs[reg] = data;
538 break;
539 }
540
541 return;
542 }
543
aspeed_ssp_intc_write(void * opaque,hwaddr offset,uint64_t data,unsigned size)544 static void aspeed_ssp_intc_write(void *opaque, hwaddr offset, uint64_t data,
545 unsigned size)
546 {
547 AspeedINTCState *s = ASPEED_INTC(opaque);
548 const char *name = object_get_typename(OBJECT(s));
549 uint32_t reg = offset >> 2;
550
551 trace_aspeed_intc_write(name, offset, size, data);
552
553 switch (reg) {
554 case R_SSPINT128_EN:
555 case R_SSPINT129_EN:
556 case R_SSPINT130_EN:
557 case R_SSPINT131_EN:
558 case R_SSPINT132_EN:
559 case R_SSPINT133_EN:
560 case R_SSPINT134_EN:
561 case R_SSPINT135_EN:
562 case R_SSPINT136_EN:
563 case R_SSPINT160_169_EN:
564 aspeed_intc_enable_handler(s, offset, data);
565 break;
566 case R_SSPINT128_STATUS:
567 case R_SSPINT129_STATUS:
568 case R_SSPINT130_STATUS:
569 case R_SSPINT131_STATUS:
570 case R_SSPINT132_STATUS:
571 case R_SSPINT133_STATUS:
572 case R_SSPINT134_STATUS:
573 case R_SSPINT135_STATUS:
574 case R_SSPINT136_STATUS:
575 aspeed_intc_status_handler(s, offset, data);
576 break;
577 case R_SSPINT160_169_STATUS:
578 aspeed_intc_status_handler_multi_outpins(s, offset, data);
579 break;
580 default:
581 s->regs[reg] = data;
582 break;
583 }
584
585 return;
586 }
587
aspeed_tsp_intc_write(void * opaque,hwaddr offset,uint64_t data,unsigned size)588 static void aspeed_tsp_intc_write(void *opaque, hwaddr offset, uint64_t data,
589 unsigned size)
590 {
591 AspeedINTCState *s = ASPEED_INTC(opaque);
592 const char *name = object_get_typename(OBJECT(s));
593 uint32_t reg = offset >> 2;
594
595 trace_aspeed_intc_write(name, offset, size, data);
596
597 switch (reg) {
598 case R_TSPINT128_EN:
599 case R_TSPINT129_EN:
600 case R_TSPINT130_EN:
601 case R_TSPINT131_EN:
602 case R_TSPINT132_EN:
603 case R_TSPINT133_EN:
604 case R_TSPINT134_EN:
605 case R_TSPINT135_EN:
606 case R_TSPINT136_EN:
607 case R_TSPINT160_169_EN:
608 aspeed_intc_enable_handler(s, offset, data);
609 break;
610 case R_TSPINT128_STATUS:
611 case R_TSPINT129_STATUS:
612 case R_TSPINT130_STATUS:
613 case R_TSPINT131_STATUS:
614 case R_TSPINT132_STATUS:
615 case R_TSPINT133_STATUS:
616 case R_TSPINT134_STATUS:
617 case R_TSPINT135_STATUS:
618 case R_TSPINT136_STATUS:
619 aspeed_intc_status_handler(s, offset, data);
620 break;
621 case R_TSPINT160_169_STATUS:
622 aspeed_intc_status_handler_multi_outpins(s, offset, data);
623 break;
624 default:
625 s->regs[reg] = data;
626 break;
627 }
628
629 return;
630 }
631
aspeed_intcio_read(void * opaque,hwaddr offset,unsigned int size)632 static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
633 unsigned int size)
634 {
635 AspeedINTCState *s = ASPEED_INTC(opaque);
636 const char *name = object_get_typename(OBJECT(s));
637 uint32_t reg = offset >> 2;
638 uint32_t value = 0;
639
640 value = s->regs[reg];
641 trace_aspeed_intc_read(name, offset, size, value);
642
643 return value;
644 }
645
aspeed_intcio_write(void * opaque,hwaddr offset,uint64_t data,unsigned size)646 static void aspeed_intcio_write(void *opaque, hwaddr offset, uint64_t data,
647 unsigned size)
648 {
649 AspeedINTCState *s = ASPEED_INTC(opaque);
650 const char *name = object_get_typename(OBJECT(s));
651 uint32_t reg = offset >> 2;
652
653 trace_aspeed_intc_write(name, offset, size, data);
654
655 switch (reg) {
656 case R_GICINT192_EN:
657 case R_GICINT193_EN:
658 case R_GICINT194_EN:
659 case R_GICINT195_EN:
660 case R_GICINT196_EN:
661 case R_GICINT197_EN:
662 aspeed_intc_enable_handler(s, offset, data);
663 break;
664 case R_GICINT192_STATUS:
665 case R_GICINT193_STATUS:
666 case R_GICINT194_STATUS:
667 case R_GICINT195_STATUS:
668 case R_GICINT196_STATUS:
669 case R_GICINT197_STATUS:
670 aspeed_intc_status_handler(s, offset, data);
671 break;
672 default:
673 s->regs[reg] = data;
674 break;
675 }
676
677 return;
678 }
679
aspeed_ssp_intcio_write(void * opaque,hwaddr offset,uint64_t data,unsigned size)680 static void aspeed_ssp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
681 unsigned size)
682 {
683 AspeedINTCState *s = ASPEED_INTC(opaque);
684 const char *name = object_get_typename(OBJECT(s));
685 uint32_t reg = offset >> 2;
686
687 trace_aspeed_intc_write(name, offset, size, data);
688
689 switch (reg) {
690 case R_SSPINT160_EN:
691 case R_SSPINT161_EN:
692 case R_SSPINT162_EN:
693 case R_SSPINT163_EN:
694 case R_SSPINT164_EN:
695 case R_SSPINT165_EN:
696 aspeed_intc_enable_handler(s, offset, data);
697 break;
698 case R_SSPINT160_STATUS:
699 case R_SSPINT161_STATUS:
700 case R_SSPINT162_STATUS:
701 case R_SSPINT163_STATUS:
702 case R_SSPINT164_STATUS:
703 case R_SSPINT165_STATUS:
704 aspeed_intc_status_handler(s, offset, data);
705 break;
706 default:
707 s->regs[reg] = data;
708 break;
709 }
710
711 return;
712 }
713
aspeed_tsp_intcio_write(void * opaque,hwaddr offset,uint64_t data,unsigned size)714 static void aspeed_tsp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
715 unsigned size)
716 {
717 AspeedINTCState *s = ASPEED_INTC(opaque);
718 const char *name = object_get_typename(OBJECT(s));
719 uint32_t reg = offset >> 2;
720
721 trace_aspeed_intc_write(name, offset, size, data);
722
723 switch (reg) {
724 case R_TSPINT160_EN:
725 case R_TSPINT161_EN:
726 case R_TSPINT162_EN:
727 case R_TSPINT163_EN:
728 case R_TSPINT164_EN:
729 case R_TSPINT165_EN:
730 aspeed_intc_enable_handler(s, offset, data);
731 break;
732 case R_TSPINT160_STATUS:
733 case R_TSPINT161_STATUS:
734 case R_TSPINT162_STATUS:
735 case R_TSPINT163_STATUS:
736 case R_TSPINT164_STATUS:
737 case R_TSPINT165_STATUS:
738 aspeed_intc_status_handler(s, offset, data);
739 break;
740 default:
741 s->regs[reg] = data;
742 break;
743 }
744
745 return;
746 }
747
748 static const MemoryRegionOps aspeed_intc_ops = {
749 .read = aspeed_intc_read,
750 .write = aspeed_intc_write,
751 .endianness = DEVICE_LITTLE_ENDIAN,
752 .valid = {
753 .min_access_size = 4,
754 .max_access_size = 4,
755 }
756 };
757
758 static const MemoryRegionOps aspeed_intcio_ops = {
759 .read = aspeed_intcio_read,
760 .write = aspeed_intcio_write,
761 .endianness = DEVICE_LITTLE_ENDIAN,
762 .valid = {
763 .min_access_size = 4,
764 .max_access_size = 4,
765 }
766 };
767
768 static const MemoryRegionOps aspeed_ssp_intc_ops = {
769 .read = aspeed_intc_read,
770 .write = aspeed_ssp_intc_write,
771 .endianness = DEVICE_LITTLE_ENDIAN,
772 .valid = {
773 .min_access_size = 4,
774 .max_access_size = 4,
775 }
776 };
777
778 static const MemoryRegionOps aspeed_ssp_intcio_ops = {
779 .read = aspeed_intcio_read,
780 .write = aspeed_ssp_intcio_write,
781 .endianness = DEVICE_LITTLE_ENDIAN,
782 .valid = {
783 .min_access_size = 4,
784 .max_access_size = 4,
785 }
786 };
787
788 static const MemoryRegionOps aspeed_tsp_intc_ops = {
789 .read = aspeed_intc_read,
790 .write = aspeed_tsp_intc_write,
791 .endianness = DEVICE_LITTLE_ENDIAN,
792 .valid = {
793 .min_access_size = 4,
794 .max_access_size = 4,
795 }
796 };
797
798 static const MemoryRegionOps aspeed_tsp_intcio_ops = {
799 .read = aspeed_intcio_read,
800 .write = aspeed_tsp_intcio_write,
801 .endianness = DEVICE_LITTLE_ENDIAN,
802 .valid = {
803 .min_access_size = 4,
804 .max_access_size = 4,
805 }
806 };
807
aspeed_intc_instance_init(Object * obj)808 static void aspeed_intc_instance_init(Object *obj)
809 {
810 AspeedINTCState *s = ASPEED_INTC(obj);
811 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
812 int i;
813
814 assert(aic->num_inpins <= ASPEED_INTC_MAX_INPINS);
815 for (i = 0; i < aic->num_inpins; i++) {
816 object_initialize_child(obj, "intc-orgates[*]", &s->orgates[i],
817 TYPE_OR_IRQ);
818 object_property_set_int(OBJECT(&s->orgates[i]), "num-lines",
819 aic->num_lines, &error_abort);
820 }
821 }
822
aspeed_intc_reset(DeviceState * dev)823 static void aspeed_intc_reset(DeviceState *dev)
824 {
825 AspeedINTCState *s = ASPEED_INTC(dev);
826 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
827
828 memset(s->regs, 0, aic->nr_regs << 2);
829 memset(s->enable, 0, sizeof(s->enable));
830 memset(s->mask, 0, sizeof(s->mask));
831 memset(s->pending, 0, sizeof(s->pending));
832 }
833
aspeed_intc_realize(DeviceState * dev,Error ** errp)834 static void aspeed_intc_realize(DeviceState *dev, Error **errp)
835 {
836 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
837 AspeedINTCState *s = ASPEED_INTC(dev);
838 AspeedINTCClass *aic = ASPEED_INTC_GET_CLASS(s);
839 int i;
840
841 memory_region_init(&s->iomem_container, OBJECT(s),
842 TYPE_ASPEED_INTC ".container", aic->mem_size);
843
844 sysbus_init_mmio(sbd, &s->iomem_container);
845
846 s->regs = g_new(uint32_t, aic->nr_regs);
847 memory_region_init_io(&s->iomem, OBJECT(s), aic->reg_ops, s,
848 TYPE_ASPEED_INTC ".regs", aic->nr_regs << 2);
849
850 memory_region_add_subregion(&s->iomem_container, aic->reg_offset,
851 &s->iomem);
852
853 qdev_init_gpio_in(dev, aspeed_intc_set_irq, aic->num_inpins);
854
855 for (i = 0; i < aic->num_inpins; i++) {
856 if (!qdev_realize(DEVICE(&s->orgates[i]), NULL, errp)) {
857 return;
858 }
859 }
860
861 for (i = 0; i < aic->num_outpins; i++) {
862 sysbus_init_irq(sbd, &s->output_pins[i]);
863 }
864 }
865
aspeed_intc_unrealize(DeviceState * dev)866 static void aspeed_intc_unrealize(DeviceState *dev)
867 {
868 AspeedINTCState *s = ASPEED_INTC(dev);
869
870 g_free(s->regs);
871 s->regs = NULL;
872 }
873
aspeed_intc_class_init(ObjectClass * klass,void * data)874 static void aspeed_intc_class_init(ObjectClass *klass, void *data)
875 {
876 DeviceClass *dc = DEVICE_CLASS(klass);
877 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
878
879 dc->desc = "ASPEED INTC Controller";
880 dc->realize = aspeed_intc_realize;
881 dc->unrealize = aspeed_intc_unrealize;
882 device_class_set_legacy_reset(dc, aspeed_intc_reset);
883 dc->vmsd = NULL;
884
885 aic->reg_ops = &aspeed_intc_ops;
886 }
887
888 static const TypeInfo aspeed_intc_info = {
889 .name = TYPE_ASPEED_INTC,
890 .parent = TYPE_SYS_BUS_DEVICE,
891 .instance_init = aspeed_intc_instance_init,
892 .instance_size = sizeof(AspeedINTCState),
893 .class_init = aspeed_intc_class_init,
894 .class_size = sizeof(AspeedINTCClass),
895 .abstract = true,
896 };
897
898 static AspeedINTCIRQ aspeed_2700_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
899 {0, 0, 10, R_GICINT192_201_EN, R_GICINT192_201_STATUS},
900 {1, 10, 1, R_GICINT128_EN, R_GICINT128_STATUS},
901 {2, 11, 1, R_GICINT129_EN, R_GICINT129_STATUS},
902 {3, 12, 1, R_GICINT130_EN, R_GICINT130_STATUS},
903 {4, 13, 1, R_GICINT131_EN, R_GICINT131_STATUS},
904 {5, 14, 1, R_GICINT132_EN, R_GICINT132_STATUS},
905 {6, 15, 1, R_GICINT133_EN, R_GICINT133_STATUS},
906 {7, 16, 1, R_GICINT134_EN, R_GICINT134_STATUS},
907 {8, 17, 1, R_GICINT135_EN, R_GICINT135_STATUS},
908 {9, 18, 1, R_GICINT136_EN, R_GICINT136_STATUS},
909 };
910
aspeed_2700_intc_class_init(ObjectClass * klass,void * data)911 static void aspeed_2700_intc_class_init(ObjectClass *klass, void *data)
912 {
913 DeviceClass *dc = DEVICE_CLASS(klass);
914 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
915
916 dc->desc = "ASPEED 2700 INTC Controller";
917 aic->num_lines = 32;
918 aic->num_inpins = 10;
919 aic->num_outpins = 19;
920 aic->mem_size = 0x4000;
921 aic->nr_regs = 0xB08 >> 2;
922 aic->reg_offset = 0x1000;
923 aic->irq_table = aspeed_2700_intc_irqs;
924 aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intc_irqs);
925 }
926
927 static const TypeInfo aspeed_2700_intc_info = {
928 .name = TYPE_ASPEED_2700_INTC,
929 .parent = TYPE_ASPEED_INTC,
930 .class_init = aspeed_2700_intc_class_init,
931 };
932
933 static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
934 {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS},
935 {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS},
936 {2, 2, 1, R_GICINT194_EN, R_GICINT194_STATUS},
937 {3, 3, 1, R_GICINT195_EN, R_GICINT195_STATUS},
938 {4, 4, 1, R_GICINT196_EN, R_GICINT196_STATUS},
939 {5, 5, 1, R_GICINT197_EN, R_GICINT197_STATUS},
940 };
941
aspeed_2700_intcio_class_init(ObjectClass * klass,void * data)942 static void aspeed_2700_intcio_class_init(ObjectClass *klass, void *data)
943 {
944 DeviceClass *dc = DEVICE_CLASS(klass);
945 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
946
947 dc->desc = "ASPEED 2700 INTC IO Controller";
948 aic->num_lines = 32;
949 aic->num_inpins = 6;
950 aic->num_outpins = 6;
951 aic->mem_size = 0x400;
952 aic->nr_regs = 0x58 >> 2;
953 aic->reg_offset = 0x100;
954 aic->reg_ops = &aspeed_intcio_ops;
955 aic->irq_table = aspeed_2700_intcio_irqs;
956 aic->irq_table_count = ARRAY_SIZE(aspeed_2700_intcio_irqs);
957 }
958
959 static const TypeInfo aspeed_2700_intcio_info = {
960 .name = TYPE_ASPEED_2700_INTCIO,
961 .parent = TYPE_ASPEED_INTC,
962 .class_init = aspeed_2700_intcio_class_init,
963 };
964
965 static AspeedINTCIRQ aspeed_2700ssp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
966 {0, 0, 10, R_SSPINT160_169_EN, R_SSPINT160_169_STATUS},
967 {1, 10, 1, R_SSPINT128_EN, R_SSPINT128_STATUS},
968 {2, 11, 1, R_SSPINT129_EN, R_SSPINT129_STATUS},
969 {3, 12, 1, R_SSPINT130_EN, R_SSPINT130_STATUS},
970 {4, 13, 1, R_SSPINT131_EN, R_SSPINT131_STATUS},
971 {5, 14, 1, R_SSPINT132_EN, R_SSPINT132_STATUS},
972 {6, 15, 1, R_SSPINT133_EN, R_SSPINT133_STATUS},
973 {7, 16, 1, R_SSPINT134_EN, R_SSPINT134_STATUS},
974 {8, 17, 1, R_SSPINT135_EN, R_SSPINT135_STATUS},
975 {9, 18, 1, R_SSPINT136_EN, R_SSPINT136_STATUS},
976 };
977
aspeed_2700ssp_intc_class_init(ObjectClass * klass,void * data)978 static void aspeed_2700ssp_intc_class_init(ObjectClass *klass, void *data)
979 {
980 DeviceClass *dc = DEVICE_CLASS(klass);
981 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
982
983 dc->desc = "ASPEED 2700 SSP INTC Controller";
984 aic->num_lines = 32;
985 aic->num_inpins = 10;
986 aic->num_outpins = 19;
987 aic->mem_size = 0x4000;
988 aic->nr_regs = 0x2B08 >> 2;
989 aic->reg_offset = 0x0;
990 aic->reg_ops = &aspeed_ssp_intc_ops;
991 aic->irq_table = aspeed_2700ssp_intc_irqs;
992 aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intc_irqs);
993 }
994
995 static const TypeInfo aspeed_2700ssp_intc_info = {
996 .name = TYPE_ASPEED_2700SSP_INTC,
997 .parent = TYPE_ASPEED_INTC,
998 .class_init = aspeed_2700ssp_intc_class_init,
999 };
1000
1001 static AspeedINTCIRQ aspeed_2700ssp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
1002 {0, 0, 1, R_SSPINT160_EN, R_SSPINT160_STATUS},
1003 {1, 1, 1, R_SSPINT161_EN, R_SSPINT161_STATUS},
1004 {2, 2, 1, R_SSPINT162_EN, R_SSPINT162_STATUS},
1005 {3, 3, 1, R_SSPINT163_EN, R_SSPINT163_STATUS},
1006 {4, 4, 1, R_SSPINT164_EN, R_SSPINT164_STATUS},
1007 {5, 5, 1, R_SSPINT165_EN, R_SSPINT165_STATUS},
1008 };
1009
aspeed_2700ssp_intcio_class_init(ObjectClass * klass,void * data)1010 static void aspeed_2700ssp_intcio_class_init(ObjectClass *klass, void *data)
1011 {
1012 DeviceClass *dc = DEVICE_CLASS(klass);
1013 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
1014
1015 dc->desc = "ASPEED 2700 SSP INTC IO Controller";
1016 aic->num_lines = 32;
1017 aic->num_inpins = 6;
1018 aic->num_outpins = 6;
1019 aic->mem_size = 0x400;
1020 aic->nr_regs = 0x1d8 >> 2;
1021 aic->reg_offset = 0;
1022 aic->reg_ops = &aspeed_ssp_intcio_ops;
1023 aic->irq_table = aspeed_2700ssp_intcio_irqs;
1024 aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intcio_irqs);
1025 }
1026
1027 static const TypeInfo aspeed_2700ssp_intcio_info = {
1028 .name = TYPE_ASPEED_2700SSP_INTCIO,
1029 .parent = TYPE_ASPEED_INTC,
1030 .class_init = aspeed_2700ssp_intcio_class_init,
1031 };
1032
1033 static AspeedINTCIRQ aspeed_2700tsp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
1034 {0, 0, 10, R_TSPINT160_169_EN, R_TSPINT160_169_STATUS},
1035 {1, 10, 1, R_TSPINT128_EN, R_TSPINT128_STATUS},
1036 {2, 11, 1, R_TSPINT129_EN, R_TSPINT129_STATUS},
1037 {3, 12, 1, R_TSPINT130_EN, R_TSPINT130_STATUS},
1038 {4, 13, 1, R_TSPINT131_EN, R_TSPINT131_STATUS},
1039 {5, 14, 1, R_TSPINT132_EN, R_TSPINT132_STATUS},
1040 {6, 15, 1, R_TSPINT133_EN, R_TSPINT133_STATUS},
1041 {7, 16, 1, R_TSPINT134_EN, R_TSPINT134_STATUS},
1042 {8, 17, 1, R_TSPINT135_EN, R_TSPINT135_STATUS},
1043 {9, 18, 1, R_TSPINT136_EN, R_TSPINT136_STATUS},
1044 };
1045
aspeed_2700tsp_intc_class_init(ObjectClass * klass,void * data)1046 static void aspeed_2700tsp_intc_class_init(ObjectClass *klass, void *data)
1047 {
1048 DeviceClass *dc = DEVICE_CLASS(klass);
1049 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
1050
1051 dc->desc = "ASPEED 2700 TSP INTC Controller";
1052 aic->num_lines = 32;
1053 aic->num_inpins = 10;
1054 aic->num_outpins = 19;
1055 aic->mem_size = 0x4000;
1056 aic->nr_regs = 0x3B08 >> 2;
1057 aic->reg_offset = 0;
1058 aic->reg_ops = &aspeed_tsp_intc_ops;
1059 aic->irq_table = aspeed_2700tsp_intc_irqs;
1060 aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intc_irqs);
1061 }
1062
1063 static const TypeInfo aspeed_2700tsp_intc_info = {
1064 .name = TYPE_ASPEED_2700TSP_INTC,
1065 .parent = TYPE_ASPEED_INTC,
1066 .class_init = aspeed_2700tsp_intc_class_init,
1067 };
1068
1069 static AspeedINTCIRQ aspeed_2700tsp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
1070 {0, 0, 1, R_TSPINT160_EN, R_TSPINT160_STATUS},
1071 {1, 1, 1, R_TSPINT161_EN, R_TSPINT161_STATUS},
1072 {2, 2, 1, R_TSPINT162_EN, R_TSPINT162_STATUS},
1073 {3, 3, 1, R_TSPINT163_EN, R_TSPINT163_STATUS},
1074 {4, 4, 1, R_TSPINT164_EN, R_TSPINT164_STATUS},
1075 {5, 5, 1, R_TSPINT165_EN, R_TSPINT165_STATUS},
1076 };
1077
aspeed_2700tsp_intcio_class_init(ObjectClass * klass,void * data)1078 static void aspeed_2700tsp_intcio_class_init(ObjectClass *klass, void *data)
1079 {
1080 DeviceClass *dc = DEVICE_CLASS(klass);
1081 AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
1082
1083 dc->desc = "ASPEED 2700 TSP INTC IO Controller";
1084 aic->num_lines = 32;
1085 aic->num_inpins = 6;
1086 aic->num_outpins = 6;
1087 aic->mem_size = 0x400;
1088 aic->nr_regs = 0x258 >> 2;
1089 aic->reg_offset = 0x0;
1090 aic->reg_ops = &aspeed_tsp_intcio_ops;
1091 aic->irq_table = aspeed_2700tsp_intcio_irqs;
1092 aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intcio_irqs);
1093 }
1094
1095 static const TypeInfo aspeed_2700tsp_intcio_info = {
1096 .name = TYPE_ASPEED_2700TSP_INTCIO,
1097 .parent = TYPE_ASPEED_INTC,
1098 .class_init = aspeed_2700tsp_intcio_class_init,
1099 };
1100
aspeed_intc_register_types(void)1101 static void aspeed_intc_register_types(void)
1102 {
1103 type_register_static(&aspeed_intc_info);
1104 type_register_static(&aspeed_2700_intc_info);
1105 type_register_static(&aspeed_2700_intcio_info);
1106 type_register_static(&aspeed_2700ssp_intc_info);
1107 type_register_static(&aspeed_2700ssp_intcio_info);
1108 type_register_static(&aspeed_2700tsp_intc_info);
1109 type_register_static(&aspeed_2700tsp_intcio_info);
1110 }
1111
1112 type_init(aspeed_intc_register_types);
1113