Searched hist:fe04b1121511a97982a1fcdd38e44d2029304a6d (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | reg_booke.h | diff fe04b1121511a97982a1fcdd38e44d2029304a6d Thu Apr 08 00:38:22 CDT 2010 Scott Wood <scottwood@freescale.com> powerpc/e500mc: Implement machine check handler.
Most of the MSCR bit assigments are different in e500mc versus
e500, and they are now write-one-to-clear.
Some e500mc machine check conditions are made recoverable (as long as
they aren't stuck on), most notably L1 instruction cache parity errors.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| H A D | cputable.h | diff fe04b1121511a97982a1fcdd38e44d2029304a6d Thu Apr 08 00:38:22 CDT 2010 Scott Wood <scottwood@freescale.com> powerpc/e500mc: Implement machine check handler.
Most of the MSCR bit assigments are different in e500mc versus
e500, and they are now write-one-to-clear.
Some e500mc machine check conditions are made recoverable (as long as
they aren't stuck on), most notably L1 instruction cache parity errors.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cputable.c | diff fe04b1121511a97982a1fcdd38e44d2029304a6d Thu Apr 08 00:38:22 CDT 2010 Scott Wood <scottwood@freescale.com> powerpc/e500mc: Implement machine check handler.
Most of the MSCR bit assigments are different in e500mc versus
e500, and they are now write-one-to-clear.
Some e500mc machine check conditions are made recoverable (as long as
they aren't stuck on), most notably L1 instruction cache parity errors.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| H A D | traps.c | diff fe04b1121511a97982a1fcdd38e44d2029304a6d Thu Apr 08 00:38:22 CDT 2010 Scott Wood <scottwood@freescale.com> powerpc/e500mc: Implement machine check handler.
Most of the MSCR bit assigments are different in e500mc versus
e500, and they are now write-one-to-clear.
Some e500mc machine check conditions are made recoverable (as long as
they aren't stuck on), most notably L1 instruction cache parity errors.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|