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/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.cdiff faa75ad9e6de20776e4629a2eb71c372b9fcfa7d Thu Nov 30 02:51:19 CST 2017 Kever Yang <kever.yang@rock-chips.com> rockchip: rk3036: fix pll config for correct frequency

There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>