Searched hist:f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | fsl_ddr_gen4.c | diff f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb Thu Sep 11 15:32:06 CDT 2014 York Sun <yorksun@freescale.com> driver/ddr/fsl: Fix DDR4 driver
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.
Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| H A D | ctrl_regs.c | diff f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb Thu Sep 11 15:32:06 CDT 2014 York Sun <yorksun@freescale.com> driver/ddr/fsl: Fix DDR4 driver
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.
Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.
Signed-off-by: York Sun <yorksun@freescale.com>
|