Searched hist:f3213d9321735aa8e252d87796d5db43d4b830ec (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe.h | diff f3213d9321735aa8e252d87796d5db43d4b830ec Tue Jan 17 10:35:54 CST 2017 Alexander Duyck <alexander.h.duyck@intel.com> ixgbe: Update driver to make use of DMA attributes in Rx path
This patch adds support for DMA_ATTR_SKIP_CPU_SYNC and
DMA_ATTR_WEAK_ORDERING. By enabling both of these for the Rx path we are
able to see performance improvements on architectures that implement either
one due to the fact that page mapping and unmapping only has to sync what
is actually being used instead of the entire buffer. In addition by
enabling the weak ordering attribute enables a performance improvement for
architectures that can associate a memory ordering with a DMA buffer such
as Sparc.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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| H A D | ixgbe_main.c | diff f3213d9321735aa8e252d87796d5db43d4b830ec Tue Jan 17 10:35:54 CST 2017 Alexander Duyck <alexander.h.duyck@intel.com> ixgbe: Update driver to make use of DMA attributes in Rx path
This patch adds support for DMA_ATTR_SKIP_CPU_SYNC and
DMA_ATTR_WEAK_ORDERING. By enabling both of these for the Rx path we are
able to see performance improvements on architectures that implement either
one due to the fact that page mapping and unmapping only has to sync what
is actually being used instead of the entire buffer. In addition by
enabling the weak ordering attribute enables a performance improvement for
architectures that can associate a memory ordering with a DMA buffer such
as Sparc.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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