Searched hist:f0f43534f7f5beb92788951da6944faad154c6a2 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/tcg/riscv/ |
| H A D | tcg-target-con-str.h | diff f0f43534f7f5beb92788951da6944faad154c6a2 Mon Apr 03 14:47:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> tcg/riscv: Simplify constraints on qemu_ld/st
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers. Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | tcg-target-con-set.h | diff f0f43534f7f5beb92788951da6944faad154c6a2 Mon Apr 03 14:47:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> tcg/riscv: Simplify constraints on qemu_ld/st
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers. Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
|
| H A D | tcg-target.c.inc | diff f0f43534f7f5beb92788951da6944faad154c6a2 Mon Apr 03 14:47:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> tcg/riscv: Simplify constraints on qemu_ld/st
The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers. Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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