Searched hist:eede7113aabd3f40f8d9c32b1690f2859fcb101a (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-tegra-periph.c | diff eede7113aabd3f40f8d9c32b1690f2859fcb101a Mon Apr 20 08:10:43 CDT 2015 Thierry Reding <treding@nvidia.com> clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| H A D | clk-tegra210.c | diff eede7113aabd3f40f8d9c32b1690f2859fcb101a Mon Apr 20 08:10:43 CDT 2015 Thierry Reding <treding@nvidia.com> clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| H A D | clk-tegra124.c | diff eede7113aabd3f40f8d9c32b1690f2859fcb101a Mon Apr 20 08:10:43 CDT 2015 Thierry Reding <treding@nvidia.com> clk: tegra: dpaux and dpaux1 are fixed factor clocks
The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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