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| H A D | i2c-exynos5.yaml | diff ea8491a28b849cd3539c7dfa20bb801cf0389915 Sat Dec 04 15:58:15 CST 2021 Sam Protsenko <semen.protsenko@linaro.org> dt-bindings: i2c: exynos5: Add bus clock
In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a
part of USIv2 block, there are two clocks provided to HSI2C controller:
- PCLK: bus clock (APB), provides access to register interface
- IPCLK: operating IP-core clock; SCL is derived from this one
Both clocks have to be asserted for HSI2C to be functional in that case.
Modify bindings doc to allow specifying bus clock in addition to
already described operating clock.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
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