Searched hist:e76e56823a318ca580be4cfc5a6a9269bc70abea (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | aspeed-clock.h | diff e76e56823a318ca580be4cfc5a6a9269bc70abea Thu Apr 26 12:22:32 CDT 2018 Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> clk:aspeed: Fix reset bits for PCI/VGA and PECI
This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.
1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-aspeed.c | diff e76e56823a318ca580be4cfc5a6a9269bc70abea Thu Apr 26 12:22:32 CDT 2018 Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> clk:aspeed: Fix reset bits for PCI/VGA and PECI
This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.
1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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