Searched hist:e48929c787ed0ebed87877c97ac90c3a47ef7dda (Results 1 – 2 of 2) sorted by relevance
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H A D | intel_iommu_internal.h | diff e48929c787ed0ebed87877c97ac90c3a47ef7dda Sun Nov 24 18:33:21 CST 2019 Qi, Yadong <yadong.qi@intel.com> intel_iommu: TM field should not be in reserved bits
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com> Signed-off-by: Qi, Yadong <yadong.qi@intel.com> Message-Id: <20191125003321.5669-3-yadong.qi@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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H A D | intel_iommu.c | diff e48929c787ed0ebed87877c97ac90c3a47ef7dda Sun Nov 24 18:33:21 CST 2019 Qi, Yadong <yadong.qi@intel.com> intel_iommu: TM field should not be in reserved bits
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com> Signed-off-by: Qi, Yadong <yadong.qi@intel.com> Message-Id: <20191125003321.5669-3-yadong.qi@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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