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| /openbmc/linux/drivers/phy/cadence/ |
| H A D | phy-cadence-torrent.c | diff e25c9dbcfc17bfe4fb0b72cdb6926db708f1ed6b Thu Mar 04 00:08:13 CST 2021 Swapnil Jakhade <sjakhade@cadence.com> phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clock
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was
expecting 10GHz clock, configuration was giving 8GHz clock. Update
register sequences to get correct PLL1 configuration.
Also, update single link PCIe and single link SGMII/QSGMII configurations
with related changes.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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