Searched hist:dccf7369652f3934456345aab6a92fa905177886 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/include/linux/ |
| H A D | pxa2xx_ssp.h | diff dccf7369652f3934456345aab6a92fa905177886 Thu Jun 04 08:55:11 CDT 2015 Jarkko Nikula <jarkko.nikula@linux.intel.com> spi: pxa2xx: Prepare for new Intel LPSS SPI type
Some of the Intel LPSS SPI properties will be different in upcoming
platforms compared to existing Lynxpoint and BayTrail/Braswell. LPSS SPI
private registers will be at different offset and there will be changes in
individual registers and default FIFO thresholds too.
Add configuration for these differences and use them in runtime based on
LPSS SSP type. With this change private registers offset autodetection
becomes needless.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
|
| /openbmc/linux/drivers/spi/ |
| H A D | spi-pxa2xx.c | diff dccf7369652f3934456345aab6a92fa905177886 Thu Jun 04 08:55:11 CDT 2015 Jarkko Nikula <jarkko.nikula@linux.intel.com> spi: pxa2xx: Prepare for new Intel LPSS SPI type
Some of the Intel LPSS SPI properties will be different in upcoming
platforms compared to existing Lynxpoint and BayTrail/Braswell. LPSS SPI
private registers will be at different offset and there will be changes in
individual registers and default FIFO thresholds too.
Add configuration for these differences and use them in runtime based on
LPSS SSP type. With this change private registers offset autodetection
becomes needless.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
|