Searched hist:d63aeb3b7ea770dac4ab13eb1e19a943a198a28d (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/tests/tcg/hexagon/ |
| H A D | reg_mut.c | d63aeb3b7ea770dac4ab13eb1e19a943a198a28d Thu Jan 05 04:23:49 CST 2023 Marco Liebel <quic_mliebel@quicinc.com> Hexagon (target/hexagon) implement mutability mask for GPRs
Some registers are defined to have immutable bits, this commit
will implement that behavior.
Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com>
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| H A D | Makefile.target | diff d63aeb3b7ea770dac4ab13eb1e19a943a198a28d Thu Jan 05 04:23:49 CST 2023 Marco Liebel <quic_mliebel@quicinc.com> Hexagon (target/hexagon) implement mutability mask for GPRs
Some registers are defined to have immutable bits, this commit
will implement that behavior.
Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com>
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| /openbmc/qemu/target/hexagon/ |
| H A D | genptr.c | diff d63aeb3b7ea770dac4ab13eb1e19a943a198a28d Thu Jan 05 04:23:49 CST 2023 Marco Liebel <quic_mliebel@quicinc.com> Hexagon (target/hexagon) implement mutability mask for GPRs
Some registers are defined to have immutable bits, this commit
will implement that behavior.
Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com>
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