Searched hist:cea0f76a483d1270ac6f6513964e3e75193dda48 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | xlnx,zynqmp-psgtr.yaml | cea0f76a483d1270ac6f6513964e3e75193dda48 Mon Jun 29 07:00:52 CDT 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
| /openbmc/linux/include/dt-bindings/phy/ |
| H A D | phy.h | diff cea0f76a483d1270ac6f6513964e3e75193dda48 Mon Jun 29 07:00:52 CDT 2020 Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|