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H A Dccs-pll.cdiff cab27256e8b3a6529faab9fc00e40fcf60b16590 Fri Jun 26 04:56:47 CDT 2020 Sakari Ailus <sakari.ailus@linux.intel.com> media: ccs-pll: Begin calculation from OP system clock frequency

The OP system clock frequency defines the CSI-2 bus clock frequency, not
the PLL output clock frequency. Both values were overwritten in the end,
but the wrong limit value was used for the OP system clock frequency,
possibly leading to too high frequencies being used.

Also remove now duplicated calculation of OP system clock frequency later
in the PLL calculator.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>