Searched hist:c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/drivers/net/dsa/microchip/ |
| H A D | lan937x.h | diff c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 Fri Sep 02 05:32:10 CDT 2022 Arun Ramadoss <arun.ramadoss@microchip.com> net: dsa: microchip: lan937x: add interrupt support for port phy link
This patch enables the interrupts for internal phy link detection for
LAN937x. The interrupt enable bits are active low. There is global
interrupt mask for each port. And each port has the individual interrupt
mask for TAS. QCI, SGMII, PTP, PHY and ACL.
The first level of interrupt domain is registered for global port
interrupt and second level of interrupt domain for the individual port
interrupts. The phy interrupt is enabled in the lan937x_mdio_register
function. Interrupt from which port is raised will be detected based on
the interrupt host data.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| H A D | lan937x_reg.h | diff c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 Fri Sep 02 05:32:10 CDT 2022 Arun Ramadoss <arun.ramadoss@microchip.com> net: dsa: microchip: lan937x: add interrupt support for port phy link
This patch enables the interrupts for internal phy link detection for
LAN937x. The interrupt enable bits are active low. There is global
interrupt mask for each port. And each port has the individual interrupt
mask for TAS. QCI, SGMII, PTP, PHY and ACL.
The first level of interrupt domain is registered for global port
interrupt and second level of interrupt domain for the individual port
interrupts. The phy interrupt is enabled in the lan937x_mdio_register
function. Interrupt from which port is raised will be detected based on
the interrupt host data.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | ksz_spi.c | diff c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 Fri Sep 02 05:32:10 CDT 2022 Arun Ramadoss <arun.ramadoss@microchip.com> net: dsa: microchip: lan937x: add interrupt support for port phy link
This patch enables the interrupts for internal phy link detection for
LAN937x. The interrupt enable bits are active low. There is global
interrupt mask for each port. And each port has the individual interrupt
mask for TAS. QCI, SGMII, PTP, PHY and ACL.
The first level of interrupt domain is registered for global port
interrupt and second level of interrupt domain for the individual port
interrupts. The phy interrupt is enabled in the lan937x_mdio_register
function. Interrupt from which port is raised will be detected based on
the interrupt host data.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | lan937x_main.c | diff c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 Fri Sep 02 05:32:10 CDT 2022 Arun Ramadoss <arun.ramadoss@microchip.com> net: dsa: microchip: lan937x: add interrupt support for port phy link
This patch enables the interrupts for internal phy link detection for
LAN937x. The interrupt enable bits are active low. There is global
interrupt mask for each port. And each port has the individual interrupt
mask for TAS. QCI, SGMII, PTP, PHY and ACL.
The first level of interrupt domain is registered for global port
interrupt and second level of interrupt domain for the individual port
interrupts. The phy interrupt is enabled in the lan937x_mdio_register
function. Interrupt from which port is raised will be detected based on
the interrupt host data.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | ksz_common.h | diff c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 Fri Sep 02 05:32:10 CDT 2022 Arun Ramadoss <arun.ramadoss@microchip.com> net: dsa: microchip: lan937x: add interrupt support for port phy link
This patch enables the interrupts for internal phy link detection for
LAN937x. The interrupt enable bits are active low. There is global
interrupt mask for each port. And each port has the individual interrupt
mask for TAS. QCI, SGMII, PTP, PHY and ACL.
The first level of interrupt domain is registered for global port
interrupt and second level of interrupt domain for the individual port
interrupts. The phy interrupt is enabled in the lan937x_mdio_register
function. Interrupt from which port is raised will be detected based on
the interrupt host data.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| H A D | ksz_common.c | diff c9cd961c0d43a22eb704aa92e1f8fb33e3d286e8 Fri Sep 02 05:32:10 CDT 2022 Arun Ramadoss <arun.ramadoss@microchip.com> net: dsa: microchip: lan937x: add interrupt support for port phy link
This patch enables the interrupts for internal phy link detection for
LAN937x. The interrupt enable bits are active low. There is global
interrupt mask for each port. And each port has the individual interrupt
mask for TAS. QCI, SGMII, PTP, PHY and ACL.
The first level of interrupt domain is registered for global port
interrupt and second level of interrupt domain for the individual port
interrupts. The phy interrupt is enabled in the lan937x_mdio_register
function. Interrupt from which port is raised will be detected based on
the interrupt host data.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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