Searched hist:c99a55d38dd5b5131f3fcbbaf41828a09ee62544 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/target/arm/ |
| H A D | cpu.c | diff c99a55d38dd5b5131f3fcbbaf41828a09ee62544 Thu Sep 07 07:54:55 CDT 2017 Portia Stephens <portia.stephens@xilinx.com> target/arm: Add Jazelle feature
This adds a feature bit indicating support of the (trivial) Jazelle
implementation if ARM_FEATURE_V6 is set or if the processor is arm926
or arm1026. This fixes the issue that any BXJ instruction will
result in an illegal_op. BXJ instructions will now check if the
architecture supports ARM_FEATURE_JAZELLE.
Signed-off-by: Portia Stephens <portia.stephens@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com
[PMM: edited commit message and comment text a bit]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
| H A D | cpu.h | diff c99a55d38dd5b5131f3fcbbaf41828a09ee62544 Thu Sep 07 07:54:55 CDT 2017 Portia Stephens <portia.stephens@xilinx.com> target/arm: Add Jazelle feature
This adds a feature bit indicating support of the (trivial) Jazelle
implementation if ARM_FEATURE_V6 is set or if the processor is arm926
or arm1026. This fixes the issue that any BXJ instruction will
result in an illegal_op. BXJ instructions will now check if the
architecture supports ARM_FEATURE_JAZELLE.
Signed-off-by: Portia Stephens <portia.stephens@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com
[PMM: edited commit message and comment text a bit]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|