Searched hist:c5d98a7b3d455204e24212cb769dec8f490e4e1c (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/target/ppc/ |
| H A D | misc_helper.c | diff c5d98a7b3d455204e24212cb769dec8f490e4e1c Thu Jun 22 04:33:52 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Add support for SMT CTRL register
A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.
Atomic serialisation operations are used to achieve this.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| H A D | helper.h | diff c5d98a7b3d455204e24212cb769dec8f490e4e1c Thu Jun 22 04:33:52 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Add support for SMT CTRL register
A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.
Atomic serialisation operations are used to achieve this.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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| H A D | translate.c | diff c5d98a7b3d455204e24212cb769dec8f490e4e1c Thu Jun 22 04:33:52 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Add support for SMT CTRL register
A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.
Atomic serialisation operations are used to achieve this.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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