Searched hist:c4ed3f04ba9defe22aa729d1646f970f791c03d7 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/x86/include/asm/uv/ |
| H A D | uv_hub.h | diff c4ed3f04ba9defe22aa729d1646f970f791c03d7 Mon Jun 08 10:44:05 CDT 2009 Jack Steiner <steiner@sgi.com> x86, UV: Fix macros for multiple coherency domains
Fix bug in the SGI UV macros that support systems with multiple
coherency domains. The macros used for referencing global MMR
(chipset registers) are failing to correctly "or" the NASID
(node identifier) bits that reside above M+N. These high bits
are supplied automatically by the chipset for memory accesses
coming from the processor socket.
However, the bits must be present for references to the special
global MMR space used to map chipset registers. (See uv_hub.h
for more details ...)
The bug results in references to invalid/incorrect nodes.
Signed-off-by: Jack Steiner <steiner@sgi.com>
Cc: <stable@kernel.org>
LKML-Reference: <20090608154405.GA16395@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
|
| /openbmc/linux/arch/x86/kernel/apic/ |
| H A D | x2apic_uv_x.c | diff c4ed3f04ba9defe22aa729d1646f970f791c03d7 Mon Jun 08 10:44:05 CDT 2009 Jack Steiner <steiner@sgi.com> x86, UV: Fix macros for multiple coherency domains
Fix bug in the SGI UV macros that support systems with multiple
coherency domains. The macros used for referencing global MMR
(chipset registers) are failing to correctly "or" the NASID
(node identifier) bits that reside above M+N. These high bits
are supplied automatically by the chipset for memory accesses
coming from the processor socket.
However, the bits must be present for references to the special
global MMR space used to map chipset registers. (See uv_hub.h
for more details ...)
The bug results in references to invalid/incorrect nodes.
Signed-off-by: Jack Steiner <steiner@sgi.com>
Cc: <stable@kernel.org>
LKML-Reference: <20090608154405.GA16395@sgi.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
|