Searched hist:bc4be0a38b63b6d4d00a58b10e164f56049be2c2 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | i915_pmu.h | diff bc4be0a38b63b6d4d00a58b10e164f56049be2c2 Fri May 19 10:49:45 CDT 2023 Tvrtko Ursulin <tvrtko.ursulin@intel.com> drm/i915/pmu: Prepare for multi-tile non-engine counters
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
v5: s/u64/u32 where needed (Ashutosh)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230519154946.3751971-7-umesh.nerlige.ramappa@intel.com
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| H A D | i915_pmu.c | diff bc4be0a38b63b6d4d00a58b10e164f56049be2c2 Fri May 19 10:49:45 CDT 2023 Tvrtko Ursulin <tvrtko.ursulin@intel.com> drm/i915/pmu: Prepare for multi-tile non-engine counters
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
v5: s/u64/u32 where needed (Ashutosh)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230519154946.3751971-7-umesh.nerlige.ramappa@intel.com
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| /openbmc/linux/include/uapi/drm/ |
| H A D | i915_drm.h | diff bc4be0a38b63b6d4d00a58b10e164f56049be2c2 Fri May 19 10:49:45 CDT 2023 Tvrtko Ursulin <tvrtko.ursulin@intel.com> drm/i915/pmu: Prepare for multi-tile non-engine counters
Reserve some bits in the counter config namespace which will carry the
tile id and prepare the code to handle this.
No per tile counters have been added yet.
v2:
- Fix checkpatch issues
- Use 4 bits for gt id in non-engine counters. Drop FIXME.
- Set MAX GTs to 4. Drop FIXME.
v3: (Ashutosh, Tvrtko)
- Drop BUG_ON that would never fire
- Make enable u64
- Pull in some code from next patch
v4: Set I915_PMU_MAX_GTS to 2 (Tvrtko)
v5: s/u64/u32 where needed (Ashutosh)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230519154946.3751971-7-umesh.nerlige.ramappa@intel.com
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