Searched hist:ba0b3a977ecf525231d36f2d9f3a6ea05c35090a (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/sound/soc/codecs/ |
| H A D | rt5677.h | diff ba0b3a977ecf525231d36f2d9f3a6ea05c35090a Tue Nov 05 19:13:35 CST 2019 Curtis Malainey <cujomalainey@chromium.org> ASoC: rt5677: Set ADC clock to use PLL and enable ASRC
Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
|
| H A D | rt5677.c | diff ba0b3a977ecf525231d36f2d9f3a6ea05c35090a Tue Nov 05 19:13:35 CST 2019 Curtis Malainey <cujomalainey@chromium.org> ASoC: rt5677: Set ADC clock to use PLL and enable ASRC
Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
|
| /openbmc/linux/sound/soc/intel/boards/ |
| H A D | bdw-rt5677.c | diff ba0b3a977ecf525231d36f2d9f3a6ea05c35090a Tue Nov 05 19:13:35 CST 2019 Curtis Malainey <cujomalainey@chromium.org> ASoC: rt5677: Set ADC clock to use PLL and enable ASRC
Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
|