Searched hist:b6ad6062f1e55bd5b9407ce89e55e3a08b83827c (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/target/arm/ |
| H A D | cpu-param.h | diff b6ad6062f1e55bd5b9407ce89e55e3a08b83827c Tue Jan 12 04:45:00 CST 2021 Rémi Denis-Courmont <remi.denis.courmont@huawei.com> target/arm: add MMU stage 1 for Secure EL2
This adds the MMU indices for EL2 stage 1 in secure state.
To keep code contained, which is largelly identical between secure and
non-secure modes, the MMU indices are reassigned. The new assignments
provide a systematic pattern with a non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| H A D | internals.h | diff b6ad6062f1e55bd5b9407ce89e55e3a08b83827c Tue Jan 12 04:45:00 CST 2021 Rémi Denis-Courmont <remi.denis.courmont@huawei.com> target/arm: add MMU stage 1 for Secure EL2
This adds the MMU indices for EL2 stage 1 in secure state.
To keep code contained, which is largelly identical between secure and
non-secure modes, the MMU indices are reassigned. The new assignments
provide a systematic pattern with a non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
| H A D | cpu.h | diff b6ad6062f1e55bd5b9407ce89e55e3a08b83827c Tue Jan 12 04:45:00 CST 2021 Rémi Denis-Courmont <remi.denis.courmont@huawei.com> target/arm: add MMU stage 1 for Secure EL2
This adds the MMU indices for EL2 stage 1 in secure state.
To keep code contained, which is largelly identical between secure and
non-secure modes, the MMU indices are reassigned. The new assignments
provide a systematic pattern with a non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| H A D | helper.c | diff b6ad6062f1e55bd5b9407ce89e55e3a08b83827c Tue Jan 12 04:45:00 CST 2021 Rémi Denis-Courmont <remi.denis.courmont@huawei.com> target/arm: add MMU stage 1 for Secure EL2
This adds the MMU indices for EL2 stage 1 in secure state.
To keep code contained, which is largelly identical between secure and
non-secure modes, the MMU indices are reassigned. The new assignments
provide a systematic pattern with a non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-8-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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