Searched hist:b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/board/freescale/mpc8572ds/ |
| H A D | tlb.c | diff b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 Tue Jan 13 15:29:28 CST 2009 Haiying Wang <Haiying.Wang@freescale.com> Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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| /openbmc/u-boot/include/configs/ |
| H A D | MPC8572DS.h | diff b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 Tue Jan 13 15:29:28 CST 2009 Haiying Wang <Haiying.Wang@freescale.com> Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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