Searched hist:ae0d7cbc99890b3a417a5705763784b8551a10d6 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/mips/include/asm/mips-boards/ |
| H A D | piix4.h | diff ae0d7cbc99890b3a417a5705763784b8551a10d6 Mon Dec 02 10:48:37 CST 2013 Paul Burton <paul.burton@imgtec.com> MIPS: Malta: mux & enable SERIRQ interrupt
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ
pin of the PIIX4 and to enable that interrupt. The kernel depends upon
the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but
previously would not configure it, instead relying upon the bootloader
having done so. If that is not the case then the typical result is that
the system appears to hang once it reaches userland as no output is
displayed on the UART.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6182/
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| /openbmc/linux/arch/mips/pci/ |
| H A D | fixup-malta.c | diff ae0d7cbc99890b3a417a5705763784b8551a10d6 Mon Dec 02 10:48:37 CST 2013 Paul Burton <paul.burton@imgtec.com> MIPS: Malta: mux & enable SERIRQ interrupt
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ
pin of the PIIX4 and to enable that interrupt. The kernel depends upon
the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but
previously would not configure it, instead relying upon the bootloader
having done so. If that is not the case then the typical result is that
the system appears to hang once it reaches userland as no output is
displayed on the UART.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6182/
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