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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | traps.c | diff a4e89ffb59235fd11d27107dea3efa4562ac0a12 Wed Jun 28 11:14:29 CDT 2017 Matt Weber <matthew.weber@rockwellcollins.com> powerpc/e6500: Update machine check for L1D cache err
This patch updates the machine check handler of Linux kernel to
handle the e6500 architecture case. In e6500 core, L1 Data Cache Write
Shadow Mode (DCWS) register is not implemented but L1 data cache always
runs in write shadow mode. So, on L1 data cache parity errors, hardware
will automatically invalidate the data cache but will still log a
machine check interrupt.
Signed-off-by: Ronak Desai <ronak.desai@rockwellcollins.com>
Signed-off-by: Matthew Weber <matthew.weber@rockwellcollins.com>
Signed-off-by: Scott Wood <oss@buserror.net>
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