Searched hist:a4544c45e109ceee87ee8c19baff28be3890d788 (Results 1 – 2 of 2) sorted by relevance
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H A D | intel_iommu_internal.h | diff a4544c45e109ceee87ee8c19baff28be3890d788 Sat Jul 04 03:07:15 CDT 2020 Liu Yi L <yi.l.liu@intel.com> intel_iommu: Use correct shift for 256 bits qi descriptor
In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced in VTD_IQA_REG. Software could set this bit to tell VT-d the QI descriptor from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should be 5 when descriptor size is 256 bits.
This patch adds the DW bit check when deciding the shift used to update VTD_IQH_REG.
Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Message-Id: <1593850035-35483-1-git-send-email-yi.l.liu@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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H A D | intel_iommu.c | diff a4544c45e109ceee87ee8c19baff28be3890d788 Sat Jul 04 03:07:15 CDT 2020 Liu Yi L <yi.l.liu@intel.com> intel_iommu: Use correct shift for 256 bits qi descriptor
In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced in VTD_IQA_REG. Software could set this bit to tell VT-d the QI descriptor from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should be 5 when descriptor size is 256 bits.
This patch adds the DW bit check when deciding the shift used to update VTD_IQH_REG.
Signed-off-by: Liu Yi L <yi.l.liu@intel.com> Message-Id: <1593850035-35483-1-git-send-email-yi.l.liu@intel.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Cc: qemu-stable@nongnu.org Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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