Searched hist:a18d783e649d761a7556f6d964efa453bb4f3a06 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/qemu/tcg/riscv/ |
| H A D | tcg-target-con-set.h | diff a18d783e649d761a7556f6d964efa453bb4f3a06 Wed Apr 26 05:59:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> tcg/riscv: Implement movcond
Implement with and without Zicond. Without Zicond, we were letting
the middle-end expand to a 5 insn sequence; better to use a branch
over a single insn.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | tcg-target.h | diff a18d783e649d761a7556f6d964efa453bb4f3a06 Wed Apr 26 05:59:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> tcg/riscv: Implement movcond
Implement with and without Zicond. Without Zicond, we were letting
the middle-end expand to a 5 insn sequence; better to use a branch
over a single insn.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| H A D | tcg-target.c.inc | diff a18d783e649d761a7556f6d964efa453bb4f3a06 Wed Apr 26 05:59:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> tcg/riscv: Implement movcond
Implement with and without Zicond. Without Zicond, we were letting
the middle-end expand to a 5 insn sequence; better to use a branch
over a single insn.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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