Searched hist:a168b8f1cde6588ff7a67699fa11e01bc77a5ddd (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/mips/mm/ |
| H A D | uasm-mips.c | diff 4f53989b0652ffe2605221c81ca8ffcfc90aed2a Tue Jun 14 08:59:38 CDT 2016 Matt Redfearn <matt.redfearn@imgtec.com> MIPS: mm: Fix definition of R6 cache instruction
Commit a168b8f1cde6 ("MIPS: mm: Add MIPS R6 instruction encodings") added
an incorrect definition of the redefined MIPSr6 cache instruction.
Executing any kernel code including this instuction results in a
reserved instruction exception and kernel panic.
Fix the instruction definition.
Fixes: a168b8f1cde6588ff7a67699fa11e01bc77a5ddd
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: <stable@vger.kernel.org> # 4.x-
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13663/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff a168b8f1cde6588ff7a67699fa11e01bc77a5ddd Wed Nov 19 03:29:42 CST 2014 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> MIPS: mm: Add MIPS R6 instruction encodings
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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| /openbmc/linux/arch/mips/include/uapi/asm/ |
| H A D | inst.h | diff a168b8f1cde6588ff7a67699fa11e01bc77a5ddd Wed Nov 19 03:29:42 CST 2014 Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> MIPS: mm: Add MIPS R6 instruction encodings
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions
so we need to take these into consideration in the micro-assembler.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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