Searched hist:"9 d843e8fafc7c0b15d8f511d146c0c3d7c816634" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/Documentation/admin-guide/ |
| H A D | ramoops.rst | diff 9d843e8fafc7c0b15d8f511d146c0c3d7c816634 Mon Mar 22 13:42:17 CDT 2021 Mukesh Ojha <mojha@codeaurora.org> pstore: Add mem_type property DT parsing support
There could be a scenario where we define some region
in normal memory and use them store to logs which is later
retrieved by bootloader during warm reset.
In this scenario, we wanted to treat this memory as normal
cacheable memory instead of default behaviour which
is an overhead. Making it cacheable could improve
performance.
This commit gives control to change mem_type from Device
tree, and also documents the value for normal memory.
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/1616438537-13719-1-git-send-email-mojha@codeaurora.org
|
| /openbmc/linux/fs/pstore/ |
| H A D | ram_core.c | diff 9d843e8fafc7c0b15d8f511d146c0c3d7c816634 Mon Mar 22 13:42:17 CDT 2021 Mukesh Ojha <mojha@codeaurora.org> pstore: Add mem_type property DT parsing support
There could be a scenario where we define some region
in normal memory and use them store to logs which is later
retrieved by bootloader during warm reset.
In this scenario, we wanted to treat this memory as normal
cacheable memory instead of default behaviour which
is an overhead. Making it cacheable could improve
performance.
This commit gives control to change mem_type from Device
tree, and also documents the value for normal memory.
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/1616438537-13719-1-git-send-email-mojha@codeaurora.org
|
| H A D | ram.c | diff 9d843e8fafc7c0b15d8f511d146c0c3d7c816634 Mon Mar 22 13:42:17 CDT 2021 Mukesh Ojha <mojha@codeaurora.org> pstore: Add mem_type property DT parsing support
There could be a scenario where we define some region
in normal memory and use them store to logs which is later
retrieved by bootloader during warm reset.
In this scenario, we wanted to treat this memory as normal
cacheable memory instead of default behaviour which
is an overhead. Making it cacheable could improve
performance.
This commit gives control to change mem_type from Device
tree, and also documents the value for normal memory.
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/r/1616438537-13719-1-git-send-email-mojha@codeaurora.org
|