Searched hist:"9 d35dc3006a9865eb5b55cc79df49933601131f8" (Results 1 – 6 of 6) sorted by relevance
| /openbmc/linux/arch/csky/mm/ |
| H A D | tlb.c | diff 9d35dc3006a9865eb5b55cc79df49933601131f8 Tue Jun 18 04:20:10 CDT 2019 Guo Ren <ren_guo@c-sky.com> csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
|
| H A D | init.c | diff 9d35dc3006a9865eb5b55cc79df49933601131f8 Tue Jun 18 04:20:10 CDT 2019 Guo Ren <ren_guo@c-sky.com> csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
|
| /openbmc/linux/arch/csky/include/asm/ |
| H A D | mmu.h | diff 9d35dc3006a9865eb5b55cc79df49933601131f8 Tue Jun 18 04:20:10 CDT 2019 Guo Ren <ren_guo@c-sky.com> csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
|
| H A D | mmu_context.h | diff 9d35dc3006a9865eb5b55cc79df49933601131f8 Tue Jun 18 04:20:10 CDT 2019 Guo Ren <ren_guo@c-sky.com> csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
|
| H A D | pgtable.h | diff 9d35dc3006a9865eb5b55cc79df49933601131f8 Tue Jun 18 04:20:10 CDT 2019 Guo Ren <ren_guo@c-sky.com> csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
|
| /openbmc/linux/arch/csky/kernel/ |
| H A D | smp.c | diff 9d35dc3006a9865eb5b55cc79df49933601131f8 Tue Jun 18 04:20:10 CDT 2019 Guo Ren <ren_guo@c-sky.com> csky: Revert mmu ASID mechanism
Current C-SKY ASID mechanism is from mips and it doesn't work well
with multi-cores. ASID per core mechanism is not suitable for C-SKY
SMP tlb maintain operations, eg: tlbi.vas need share the same asid
in all processors and it'll invalid the tlb entry in all cores with
the same asid.
This patch is prepare for new ASID mechanism.
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Arnd Bergmann <arnd@arndb.de>
|