"97840b5d1fe0960134c3553a9d9d1c1cd1be784d" (history) in projects: openbmc

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/openbmc/u-boot/arch/arm/lib/
H A D	cache-cp15.c	`diff 97840b5d1fe0960134c3553a9d9d1c1cd1be784d Tue Mar 24 11:25:12 CDT 2015 Bryan Brinsko <bryan.brinsko@rockwellcollins.com> ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>`
/openbmc/u-boot/arch/arm/include/asm/
H A D	system.h	`diff 97840b5d1fe0960134c3553a9d9d1c1cd1be784d Tue Mar 24 11:25:12 CDT 2015 Bryan Brinsko <bryan.brinsko@rockwellcollins.com> ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>`