"8936691ba69bc322201c62e977e2803cfe67fc40" (history) in projects: openbmc

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/openbmc/u-boot/drivers/ddr/fsl/
H A D	ctrl_regs.c	`diff 8936691ba69bc322201c62e977e2803cfe67fc40 Fri Jul 29 11:02:29 CDT 2016 York Sun <york.sun@nxp.com> driver/ddr/fsl: Fix timing_cfg_2 Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>`