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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | i915_irq.c | diff 8692d00e996ed2a6560702623e5cb646da0f9767 Sat Feb 05 04:08:21 CST 2011 Chris Wilson <chris@chris-wilson.co.uk> drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"
I stumbled over this magic bit in the gen3 INSTPM:
Bit11 Interrupt-Based AGPBUSY# Enable:
‘0’ = Pending GMCH interrupts will not cause AGPBUSY# assertion.
‘1’ = Pending GMCH interrupts will cause AGPBUSY# assertion and hence
can cause the CPU to exit C3. There is no suppression of cacheable
writes.
Note that in either case in C3 the interrupts are not lost. They will be
forwarded to the ICH when the GMCH is out of C3.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@kernel.org
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| H A D | i915_reg.h | diff 8692d00e996ed2a6560702623e5cb646da0f9767 Sat Feb 05 04:08:21 CST 2011 Chris Wilson <chris@chris-wilson.co.uk> drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"
I stumbled over this magic bit in the gen3 INSTPM:
Bit11 Interrupt-Based AGPBUSY# Enable:
‘0’ = Pending GMCH interrupts will not cause AGPBUSY# assertion.
‘1’ = Pending GMCH interrupts will cause AGPBUSY# assertion and hence
can cause the CPU to exit C3. There is no suppression of cacheable
writes.
Note that in either case in C3 the interrupts are not lost. They will be
forwarded to the ICH when the GMCH is out of C3.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@kernel.org
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