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| /openbmc/qemu/hw/riscv/ |
| H A D | boot.c | diff 8590f53661ec678fd3aa97b4da212b0c00056c2e Wed Jul 01 13:39:49 CDT 2020 Atish Patra <atish.patra@wdc.com> RISC-V: Support 64 bit start address
Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.
Update the ROM code correctly to reflect the 64bit value.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-5-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| H A D | sifive_u.c | diff 8590f53661ec678fd3aa97b4da212b0c00056c2e Wed Jul 01 13:39:49 CDT 2020 Atish Patra <atish.patra@wdc.com> RISC-V: Support 64 bit start address
Even though the start address in ROM code is declared as a 64 bit address
for RV64, it can't be used as upper bits are set to zero in ROM code.
Update the ROM code correctly to reflect the 64bit value.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20200701183949.398134-5-atish.patra@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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