Searched hist:"806 ab537ac4705bcf0c577382f0e3f90c6edcd14" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/sd/ |
| H A D | sdhci.h | diff 806ab537ac4705bcf0c577382f0e3f90c6edcd14 Thu Nov 14 03:48:38 CST 2024 Jamin Lin <jamin_lin@aspeedtech.com> hw/sd/sdhci: Introduce a new Write Protected pin inverted property
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some boards are
design Write Protected pin active high. In other words, write enable the bit 19
should be 0 and write protected the bit 19 should be 1 at the
Present State Register (0x24). To support it, introduces a new "wp-inverted"
property and set it false by default.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
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| /openbmc/qemu/hw/sd/ |
| H A D | sdhci.c | diff 806ab537ac4705bcf0c577382f0e3f90c6edcd14 Thu Nov 14 03:48:38 CST 2024 Jamin Lin <jamin_lin@aspeedtech.com> hw/sd/sdhci: Introduce a new Write Protected pin inverted property
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some boards are
design Write Protected pin active high. In other words, write enable the bit 19
should be 0 and write protected the bit 19 should be 1 at the
Present State Register (0x24). To support it, introduces a new "wp-inverted"
property and set it false by default.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Acked-by: Cédric Le Goater <clg@redhat.com>
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